LOW-VOLTAGE TO HIGH-VOLTAGE LEVEL TRANSLATION USING CAPACITIVE COUPLING

• US 20110316586A1
• Filed: 06/25/2010
• Published: 12/29/2011
• Est. Priority Date: 06/25/2010
• Status: Active Grant

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Inventors: KNIERIM, DAVID L.
• Granted Patent: US 8,149,017 B2
• Time in Patent Office: Days
• US Class Current: 326/80
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit

Abstract

A voltage level translator circuit has a digital logic circuit having a digital logic signal at least one high-voltage capacitor having a first and second connection, wherein one of the first and second connections is electrically coupled to the digital logic signal, and a cross-coupled inverter pair having, the output of at least one inverter of the pair electrically coupled to the other connection of the at least one high-voltage capacitor. A high-voltage driving circuit has two low-voltage input signals, two high-voltage output signals, a first signal being a high-side drive signal and a second signal being a low-side drive signal, two level translators, a first level translator corresponding to the high-side drive signal, and a second level translator corresponding to the low-side drive signal, the level translators including a digital logic circuit having a digital logic signal, at least one high-voltage capacitor having a first and second connection, wherein one of the first and second connections is electrically coupled to the digital logic signal, and a cross-coupled inverter pair having, the output of at least one inverter of the pair electrically coupled to the other connection of the at least one high-voltage capacitor.

Claims

1. A voltage level translator circuit, comprising:

a digital logic circuit having a digital logic signal;

first and second high voltage capacitors, each having a first and second connection, wherein the second capacitor has the first connection has an electrical coupling to the digital logic signal and the electrical coupling includes logic inversion;

a cross-coupled inverter pair having the output of at least one inverter of the pair electrically coupled to the other connection of the at least one high-voltage capacitor, wherein the second capacitor has the second connection electrically coupled to an output of the other of the at least one inverter of the pair; and

a sensing circuit configured to sense the state of the cross-coupled inverter pair and to produce an output signal having a voltage level higher than the digital logic signal.

3. The voltage level translator circuit of claim 1, wherein the at least one inverter of the cross-coupled inverter pair is weak by having high impedance relative to an impedance of the digital logic signal.

4. The voltage level translator circuit of claim 1, wherein the cross-coupled inverter pair receives a reduced supply voltage compared to a supply voltage for the digital logic circuit.

2. (canceled)

5. (canceled)

8. The voltage translator circuit of claim 5, further comprising a pseudo-differential receiver circuit arranged to sense a latch state of the cross-coupled inverter pair.

6. (canceled)

7. (canceled)

9. A high-voltage driving circuit, comprising:

two low-voltage input signals;

two high-voltage output signals, a first signal being a high-side drive signal and a second signal being a low-side drive signal;

two level translators, a first level translator generating the high-side drive signal, and a second level translator generating the low-side drive signal, the level translators comprising;

a digital logic circuit having a digital logic signal;

at least one high-voltage capacitor having a first and second connection, wherein one of the first and second connections is electrically coupled to the digital logic signal; and

a cross-coupled inverter pair having the output of at least one inverter of the pair electrically coupled to the other connection of the at least one high-voltage capacitor.

10. The high-voltage driving circuit of claim 9, the level translators further comprising a sensing circuit configured to sense the state of the cross-coupled inverter pair.

11. The high-voltage driving circuit of claim 10, the level translators further comprising a buffer configured to buffer an output of the sensing circuit.

12. The high-voltage driving circuit of claim 9, wherein the at least one inverter of the cross-coupled inverter pair is weak by having high impedance relative to an impedance of the digital logic signal.

13. The high-voltage driving circuit of claim 9, wherein the at least one high-voltage capacitor comprises first and second capacitors.

14. The high-voltage driving circuit of claim 13, wherein the second capacitor has a first connection electrically coupled to the digital logic signal and a second connection electrically coupled to an output of the other of the at least one inverter of the pair.

15. The high-voltage driving circuit of claim 14, wherein the electrical coupling of the digital logic signal to the first connection of the second capacitor includes logic inversion.

16. The high-voltage driving circuit of claim 13, further comprising a pseudo-differential receiver circuit arranged to sense a latch state of the cross-coupled inverter pair.

17. The high-voltage driving circuit of claim 9, further comprising a cross-conduction prevention circuit configured to detect simultaneous enabling of both the high-side drive signal and the low-side drive signal.

18. The high-voltage driving circuit of claim 17, wherein an output of the cross-conduction prevention circuit resets an output of one of either the high-side level translator or the low-side level translator to an off state.

19. The high-voltage driving circuit of claim 9, further comprising a power-on reset circuit to reset outputs of one of either the high-side level translator or the low-side level translator to an off state as power is applied to the circuit.