PHASE LOCKING FOR MULTIPLE SERIAL INTERFACES

• US 20110316596A1
• Filed: 12/22/2008
• Published: 12/29/2011
• Est. Priority Date: 12/22/2008
• Status: Active Grant

• Current Assignee: Thomson Licensing (Vantiva SA)
• Original Assignee: Thomson Licensing (Vantiva SA)
• Inventors: Schultz, Mark Alan
• Granted Patent: US 9,148,279 B2
• Time in Patent Office: Days
• US Class Current: 327/156
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

An arrangement is described which reduces the number of phase locked loops (PLLs) required in a typical high speed serial interface system. A reference clock is sent from a transmitter on a main board to a receiver on a system board, which employs a PLL that also drives a transmitter on the system board. The transmitter on the system board transmits a data signal to a receiver on the main board which does not require a PLL. Rather, the receiver on the main board is clocked with a static-phase, master reference clock, and the phase of the reference clock sent from the main board is controlled so as to achieve synchronism of the data signal received by the main board receiver using the static-phase, master reference clock. In this way, each high speed serial interface loop between the main board and the individual system boards is controllably adjusted in phase, compensating for interconnection path lengths and providing synchronism between the received signal and the common, static-phase, master reference clock which supplies all the main controller board receivers.

Claims

1. An apparatus comprising:

a bidirectional low-voltage differential signaling interface coupled between first and second terminals each having a receiver and a transmitter for data communication;

a phase locked loop coupled to said second receiver and to said second transmitter at said second terminal;

a sync word generator forming a sync word for transmission by said second transmitter;

a reference clock coupled to said first receiver at said first terminal; and

a phase selector for selecting a phase of a signal derived from said reference clock, said selected phase signal being coupled to said first transmitter and communicated to said phase locked loop for synchronizing said second receiver and said second transmitter, said phase selector being controlled responsive to said sync word received by said first receiver from said second transmitter.

2. The apparatus of claim 1, comprising a first state machine coupled to said sync word generator and controlling said sync word generation.

3. The apparatus of claim 2, wherein generation of said sync word occurs during source data absence.

4. The apparatus of claim 2, wherein generation of said sync word occurs at each transport packet.

5. The apparatus of claim 1, comprising a second state machine coupled to said first receiver for monitoring said sync word received by said first receiver, wherein said second state machine controls said phase selector to change said signal phase so as to receive said sync word without error.

6. The apparatus of claim 5, wherein said first receiver is supplied with a constant phase reference signal.

7. The apparatus of claim 1, comprising:

a further bidirectional LVDS interface coupled between third and fourth terminals each having a receiver and a transmitter for data communication;

a further PLL coupled to said fourth receiver and to said fourth transmitter at said fourth terminal;

a further sync word generator coupled to add a sync word to data for transmission by said fourth transmitter; and

a further phase selector for selecting a phase of a further signal derived from said reference clock, said further selected phase signal being coupled to said third transmitter and communicated to said further PLL for synchronizing said fourth receiver and said fourth transmitter, said further phase selector being controlled responsive to said further sync word received by said third receiver from said fourth transmitter,

wherein the reference clock is coupled to said third receiver for decoding said sync word.

8. The apparatus of claim 7, wherein said first and third terminals are on the same board.

9. The apparatus of claim 7, wherein said second and fourth terminals are on different boards.

10. The apparatus of claim 7, wherein a length of the LVDS interface and a length of the further LVDS interface are different.

11. The apparatus of claim 7, wherein said phase of the selected phase signal and said phase of the further selected phase signal are different.

12. The apparatus of claim 1, wherein said sync word comprises a predefined sequence of bits.

13. A method comprising:

transmitting a first clock signal from a first terminal to a second terminal;

adding a sync signal to data for transmission;

transmitting the data and sync signal from the second terminal to the first terminal in accordance with the first clock signal;

receiving the data and sync signal at the first terminal in accordance with a second clock signal; and

controlling a phase of the first clock signal to synchronize data received at the first terminal with the second clock signal, the phase of the first clock signal being controlled responsive to the sync signal received by said first terminal.

14. The method of claim 13, comprising;

controlling the phase of the first clock signal to receive the sync signal without error.

15. The method of claim 13, comprising:

transmitting a third clock signal from a third terminal to a fourth terminal;

adding a sync signal to data for transmission by said fourth terminal;

transmitting the data from the fourth terminal to the third terminal in accordance with the third clock signal;

receiving the data at the third terminal in accordance with the second clock signal; and

controlling a phase of the third clock signal so that the data received at the third terminal is in synchronization with the second clock signal, said phase of the third clock signal being controlled responsive to said sync signal received by said third terminal.

16. The method of claim 15, wherein the first and third terminals are on the same board and the second and fourth terminals are on different boards.

17. The method of claim 15, wherein the phase of the first clock signal and the phase of the third clock signal are different.

18. The method of claim 15, wherein the sync signal comprises a predefined sequence of bits.