PLANAR PHASE-CHANGE MEMORY CELL WITH PARALLEL ELECTRICAL PATHS

• US 20110317481A1
• Filed: 06/25/2010
• Published: 12/29/2011
• Est. Priority Date: 06/25/2010
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Franceschini, Michele M., Karidis, John P.
• Granted Patent: US 8,624,217 B2
• Time in Patent Office: Days
• US Class Current: 365/163
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0083 Write to perform initialising, forming process, electro forming or conditioning
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

A planar phase change memory cell with parallel electrical paths. The memory cell includes a first conductive electrode region having a length greater than its width and an axis aligned with the length. The memory cell also includes a second conductive electrode region having an edge oriented at an angle to the axis of the first conductive electrode region. The memory cell further includes an insulator region providing a lateral separation distance between an end of the first conductive electrode region and the edge of the second conductive electrode region, the insulator region including at least part of an insulator film and the lateral separation distance is responsive to the thickness of the insulator film.

Claims

1. An integrated electronic apparatus, having a substantially planar surface comprising:

a first conductive electrode region having a length greater than its width and an axis aligned with the length;

a second conductive electrode region having an edge oriented at an angle to the axis of the first conductive electrode region; and

an insulator region providing a lateral separation distance between an end of the first conductive electrode region and the edge of the second conductive electrode region, the insulator region comprising at least part of an insulator film and the lateral separation distance is responsive to the thickness of the insulator film.

2. The apparatus of claim 1, wherein the width of the first conductive electrode region is responsive to a thickness of a first deposited material layer.

3. The apparatus of claim 2, wherein the first deposited material layer is one or titanium, tungsten, titanium nitride, and titanium aluminum nitride

4. The apparatus of claim 1, further comprising a layer of a storage material that at least partially covers the first conductive electrode region and the second conductive electrode region.

5. The apparatus of claim 4, wherein the storage material is a phase change material.

6. The apparatus of claim 4, wherein the layer of a storage material is patterned.

7. The apparatus of claim 1, wherein the angle is substantially a right angle.

8. The apparatus of claim 1, wherein the angle is between 20 and 80 degrees.

9. A method for operating a phase change memory, the method comprising:

initializing a memory cell, the memory cell comprising a first conductive electrode having a length greater than its width and an axis aligned with the length, a second conductive electrode having an edge oriented at an angle to the axis of the first conductive electrode, an insulator providing a separation distance between an end of the first conductive electrode and the edge of the second conductive electrode, and a phase change material covering a substantial portion of the first conductive electrode and at least a portion of the second conductive electrode, the initializing comprising;

creating a first amorphous material region in the phase change material, the first amorphous material region covering a substantial area of the phase change material;

creating an active crystalline material region inside the first amorphous material region by crystallizing a portion of the first amorphous material region; and

storing information in the memory cell by creating a second amorphous material region inside the active crystalline material region.

10. The method of claim 9 further comprising:

applying an electrical pulse larger than subsequently applied electrical pulses to the memory cell, the applying the electrical pulse via at least one of the first conductive electrode and the second conductive electrode.

11. The method of claim 9, wherein the memory cell is a single level cell.

12. The method of claim 9, wherein the memory cell is a multiple level cell.

13. The method of claim 9, wherein the creating an active crystalline material region inside the first amorphous material region further comprises adjusting a size of the active crystalline material region to obtain a specified cell resistance.

14. A method of manufacturing a phase change memory cell on a substrate, the method comprising:

etching a first trench in the substrate;

depositing a first conductor layer in the first trench;

depositing a first insulator layer over the first conductor layer in the first trench;

etching a second trench in the substrate at an angle to the first trench;

depositing a second insulator layer in the second trench;

depositing a second conductor layer over the second insulator layer in the second trench; and

depositing phase change material, the phase change material in contact with the first conductor layer and the second conductor layer.

15. The method of claim 14, wherein the substrate is a wafer including a bottom contact for providing access to the phase change memory cell and wherein the etching a first trench in the substrate exposes the bottom contact.

16. The method of claim 14, wherein at least one of the first trench and the second trench is not straight.

17. The method of claim 14, wherein the first insulator layer fills the first trench.

18. The method of claim 14, wherein the second conductor layer fills the second trench.

19. The method of claim 14, wherein the second conductor layer does not fill the second trench and the method further comprises depositing a third insulator layer in the second trench to fill the second trench.

20. A method for operating a phase change memory cell, the method comprising:

changing the size of an amorphous material region in a phase change material using one or more electrical pulses;

the phase change memory cell comprising a first conductive electrode having a length greater than its width and an axis aligned with the length, a second conductive electrode having an edge oriented at an angle to the axis of the first conductive electrode, an insulator providing a separation distance between an end of the first conductive electrode and the edge of the second conductive electrode; and

the phase change material covering at least a portion of the first conductive electrode and the second conductive electrode.

21. The method of claim 20, wherein:

the increasing the size of amorphous phase change material region comprises applying a first electrical pulse, the applying the first electrical pulse via at least one of the first conductive electrode and the second conductive electrode, the first electrical pulse having at least one of an amplitude larger than a previously applied electrical pulse and a duration shorter than a previously applied electrical pulse; and

22. The method of claim 20, wherein:

the decreasing the size of amorphous phase change material region comprises applying a second electrical pulse to the memory cell, the applying the second electrical pulse via at least one of the first conductive electrode and the second conductive electrode, the second electrical pulse having at least one of an amplitude lower than the previously applied electrical pulse and a duration longer than the previously applied electrical pulse.

23. A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure having a substantially planar surface, the design structure comprising:

a first conductive electrode region having a length greater than its width and an axis aligned with the length;

a second conductive electrode region having an edge oriented at an angle to the axis of the first conductive electrode region; and

an insulator region providing a lateral separation distance between an end of the first conductive electrode region and the edge of the second conductive electrode region, the insulator region comprising at least part of an insulator film and the lateral separation distance is responsive to the thickness of the insulator film.

24. The design structure of claim 23, further comprising a layer of a storage material that at least partially covers the first conductive electrode and the second conductive electrode.

25. The design structure of claim 24, wherein the storage material is a phase change material.