JAM LATCH FOR LATCHING MEMORY ARRAY OUTPUT DATA

• US 20110317496A1
• Filed: 06/23/2010
• Published: 12/29/2011
• Est. Priority Date: 06/23/2010
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bunce, Paul A., Davis, John D., Henderson, Diana M., Vora, Jigar
• Granted Patent: US 8,351,278 B2
• Time in Patent Office: Days
• US Class Current: 365/189.05
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/106 Data output latches

Abstract

A jam latch device for a data node includes a feed forward inverter having an input coupled to the data node; a feedback inverter having an input connected to an output of the feed forward inverter with an output of the feedback inverter connected to the data node; an isolation device that selectively decouples the feedback inverter from a power supply rail, the isolation device controlled by a clock signal of a reset device that resets the data node to a first logic state such that decoupling of the feedback inverter from the power supply rail coincides with resetting the data node to the first logic state; and a margin test device that selectively increases pull down strength of the feedback inverter.

Claims

1. A jam latch device for a data node, comprising:

a feed forward inverter having an input coupled to the data node;

a feedback inverter having an input connected to an output of the feed forward inverter with an output of the feedback inverter connected to the data node; and

an isolation device that selectively decouples the feedback inverter from a first power supply rail, the isolation device controlled by a clock signal of a reset device that resets the data node to a first logic state such that decoupling of the feedback inverter from the first power supply rail coincides with resetting the data node to the first logic state;

wherein the data node comprises an output node of a memory array.

2. The device of claim 1, wherein the isolation device comprises a p-type field effect transistor (PFET) header connected between the first power supply rail and the feedback inverter.

3. The device of claim 2, wherein the reset device comprises a first n-type field effect transistor (NFET) that resets the data output node to a logic low state.

4. The device of claim 1, wherein the margin test device comprises a second NFET connected between the feedback inverter and a second power supply rail.

5. The device of claim 4, further comprising a fully-on connected NFET in parallel with the second NFET.

6. The device of claim 1, further comprising a margin test device that selectively increases pull down strength of the feedback inverter.

7. An output control circuit for a memory array, comprising:

a data output node that is precharged to a first logic state prior to a read operation and prior to a write operation of the memory array;

logic configured to selectively couple memory cell data to the data output node during a memory evaluate operation; and

a jam latch device for latching memory cell data on the data output node, the jam latch device further comprising;

a feed forward inverter having an input coupled to the data output node;

a feedback inverter having an input connected to an output of the feed forward inverter with an output of the feedback inverter connected to the data output node; and

an isolation device that selectively decouples the feedback inverter from a first power supply rail, the isolation device controlled by a clock signal of a reset device that resets the data output node to a first logic state prior to the memory evaluate operation such that decoupling of the feedback inverter from the first power supply rail coincides with resetting the data output node to the first logic state.

8. The circuit of claim 7, wherein the isolation device comprises a p-type field effect transistor (PFET) header connected between the first power supply rail and the feedback inverter.

9. The circuit of claim 8, wherein the reset device comprises a first n-type field effect transistor (NFET) that resets the data output node to a logic low state.

10. The circuit of claim 9, further comprising a margin test device that selectively increases pull down strength of the feedback inverter.

11. The circuit of claim 10, wherein the margin test device comprises a second NFET connected between the feedback inverter and a second power supply rail.

12. The circuit of claim 11, further comprising a fully-on connected NFET in parallel with the second NFET.

13. A method of latching a data output node, the method comprising:

coupling an input of a feed forward inverter to the data node;

coupling an output of the feed forward inverter to an input of a feedback inverter, with an output of the feedback inverter connected to the data node; and

selectively decoupling, with an isolation device, the feedback inverter from a first power supply rail, the isolation device controlled by a clock signal of a reset device that resets the data node to a first logic state such that decoupling of the feedback inverter from the first power supply rail coincides with resetting the data node to the first logic state.

14. The method of claim 13, wherein the isolation device comprises a p-type field effect transistor (PFET) header connected between the first power supply rail and the feedback inverter.

15. The method of claim 14, wherein the reset device comprises a first n-type field effect transistor (NFET) that resets the data output node to a logic low state.

16. The method of claim 15, further comprising configuring a margin test device that selectively increases pull down strength of the feedback inverter.

17. The method of claim 16, wherein the margin test device comprises a second NFET connected between the feedback inverter and a second power supply rail.

18. The method of claim 17, further comprising configuring a fully-on connected NFET in parallel with the second NFET.

19. The method of claim 13, wherein the data node comprises an output node of a memory array.