Etch process for reducing silicon recess

• US 20110318936A1
• Filed: 06/29/2010
• Published: 12/29/2011
• Est. Priority Date: 06/29/2010
• Status: Active Grant

• Current Assignee: Tokyo Electron Limited
• Original Assignee: Tokyo Electron Limited
• Inventors: KO, Akiteru, COLE, Christopher
• Granted Patent: US 8,268,184 B2
• Time in Patent Office: Days
• US Class Current: 438/724
• CPC Class Codes: H01J 37/32091 the radio frequency energy being capacitively coupled to the plasma
• CPC Class Codes: H01J 37/321 the radio frequency energy being inductively coupled to the plasma
• CPC Class Codes: H01J 37/3266 Magnetic control means
• CPC Class Codes: H01J 37/32724 Temperature
• CPC Class Codes: H01L 21/31116 by dry-etching

Abstract

A method for selectively etching a substrate is described. The method includes disposing a substrate comprising a silicon nitride (SiN_y) layer overlying silicon in a plasma etching system, and transferring a pattern to the silicon nitride layer using a plasma etch process, wherein the plasma etch process utilizes a process composition having as incipient ingredients a process gas containing C, H and F, and an additive gas including CO₂. The method further includes: selecting an amount of the additive gas in the plasma etch process to achieve: (1) a silicon recess formed in the silicon having a depth less than 10 nanometers (nm), and (2) a sidewall profile in the pattern having an angular deviation from 90 degrees less than 2 degrees.

Claims

1. A method for selectively etching a substrate, comprising:

disposing a substrate comprising a silicon nitride (SiN_y) layer overlying silicon in a plasma etching system;

transferring a pattern to said silicon nitride layer using a plasma etch process, wherein said plasma etch process utilizes a process gas composition having as incipient ingredients a process gas containing C, H and F, and an additive gas including CO₂; and

selecting an amount of said additive gas in said plasma etch process to achieve;

(1) a silicon recess formed in said silicon having a depth less than 10 nanometers (nm), and (2) a sidewall profile in said pattern having an angular deviation from 90 degrees less than 2 degrees.

2. The method of claim 1, further comprising:

extending said plasma etch process by an over-etch period of time to uniformly transfer said pattern to said silicon nitride layer on said substrate.

3. The method of claim 1, wherein said process gas containing C, H and F comprises CHF₃, CH₃F, or CH₂F₂, or any combination of two or more thereof.

4. The method of claim 1, wherein said process gas containing C, H and F consists of CHF₃.

5. The method of claim 1, wherein said process gas composition further comprises a noble gas.

6. The method of claim 1, wherein said process gas composition further comprises an oxygen containing gas, said oxygen containing gas comprises oxygen (O₂), CO, NO, N₂O, or NO₂, or any combination thereof.

7. The method of claim 1, wherein said process gas composition consists of CHF₃, CO₂, and Ar.

8. The method of claim 1, wherein said silicon recess is less than 8 nm.

9. The method of claim 1, wherein said angular deviation is less than 1 degree.

10. The method of claim 1, wherein said plasma etch process includes setting a pressure in said plasma etching system ranging from 30 mTorr to 60 mTorr.

11. The method of claim 1, wherein a flow rate of said process gas containing C, H and F ranges from about 10 sccm to about 50 sccm.

12. The method of claim 1, wherein a flow rate of said additive gas ranges from about 1 sccm to about 10 sccm.

13. The method of claim 1, wherein said plasma etch process includes coupling first radio frequency (RF) power at a first frequency to a substrate holder upon which said substrate rests in said plasma etching system, and coupling second radio frequency (RF) power at a second frequency to an upper electrode opposing said substrate on said substrate holder.

14. The method of claim 13, wherein said first radio frequency (RF) power ranges up to 500 W, and said second radio frequency (RF) power ranges up to 500 W.

15. The method of claim 1, wherein a ratio between a flow rate of said additive gas and a flow rate of said process gas containing C, H and F ranges from 5% to 25%.

16. The method of claim 1, wherein a ratio between a flow rate of said additive gas and a flow rate of said process gas containing C, H and F ranges from 15% to 20%.

17. The method of claim 1, wherein said process gas containing C, H and F consists of CHF₃, and wherein a ratio between a flow rate of said CO₂ and a flow rate of said CHF₃ ranges from 15% to 20%.

18. The method of claim 1, wherein said substrate rest on a temperature controlled substrate holder in said plasma etching system, said temperature controlled substrate holder comprises:

a support base having fluid channels to circulate a temperature controlled thermal fluid in said support base; and

a substrate support coupled via a thermal insulator to an upper portion of said support base, said substrate support comprising;

one or more heating elements embedded within said substrate support,

an upper surface to support said substrate by contact between said upper surface and a backside of said substrate, and

an electrostatic clamp electrode to hold said substrate on said upper surface of said substrate support.

19. The method of claim 18, wherein said temperature controlled substrate holder further comprises:

a backside gas supply system configured to supply a heat transfer gas to the backside of said substrate through at least one of a plurality of orifices or channels disposed on said upper surface of said substrate support, wherein said plurality of orifices of said backside gas supply system are arranged in a plurality of zones on said upper surface of said substrate support to vary a backside pressure in a radial direction between a substantially central region of the backside of said substrate and a substantially edge region of the backside of said substrate.

20. The method of claim 1, wherein said silicon nitride layer is part of an insulation spacer for a transistor gate.