DMA-BASED ACCELERATION OF COMMAND PUSH BUFFER BETWEEN HOST AND TARGET DEVICES

• US 20110320724A1
• Filed: 06/28/2010
• Published: 12/29/2011
• Est. Priority Date: 06/28/2010
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Mejdrich, Eric O., Schardt, Paul E., Shearer, Robert A., Tubbs, Matthew R.
• Granted Patent: US 8,719,455 B2
• Time in Patent Office: Days
• US Class Current: 711/125
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

Direct Memory Access (DMA) is used in connection with passing commands between a host device and a target device coupled via a push buffer. Commands passed to a push buffer by a host device may be accumulated by the host device prior to forwarding the commands to the push buffer, such that DMA may be used to collectively pass a block of commands to the push buffer. In addition, a host device may utilize DMA to pass command parameters for commands to a command buffer that is accessible by the target device but is separate from the push buffer, with the commands that are passed to the push buffer including pointers to the associated command parameters in the command buffer.

Claims

1. A circuit arrangement, comprising:

a push buffer configured to store pending commands to be processed by a target device;

a host interface processor disposed in the target device and configured to retrieve pending commands from the push buffer and initiate processing of the commands by the target device; and

control logic configured to accumulate a plurality of commands from the host device and perform a collective operation to store the accumulated plurality of commands in the push buffer.

2. The circuit arrangement of claim 1, wherein the push buffer comprises a circular queue including a plurality of entries and head and tail pointers pointing to selected entries in the push buffer, wherein the push buffer is resident in a shared memory accessible by the host and target devices, and wherein the control logic is resident in the host device and includes a device driver for the target device.

4. The circuit arrangement of claim 1, wherein the host interface processor is configured to sequentially and individually pull commands out of the push buffer and update a pointer in the push buffer as commands are pulled from the push buffer.

5. The circuit arrangement of claim 1, wherein the control logic is configured to accumulate the plurality of commands in a block, and wherein the control logic includes Direct Memory Access (DMA) logic configured to write the block of accumulated plurality of commands to the push buffer.

6. The circuit arrangement of claim 1, wherein the control logic is configured to update a pointer in the push buffer after storing the accumulated plurality of commands in the push buffer to notify the host interface processor of the addition of the plurality of commands to the push buffer.

7. The circuit arrangement of claim 1, further comprising a command buffer configured to store parameter data for a first command from among the accumulated plurality of commands, wherein the control logic is configured to store, along with the first command in the push buffer, a pointer to the parameter data in the command buffer.

8. The circuit arrangement of claim 7, wherein the control logic includes Direct Memory Access (DMA) logic configured to write the parameter data for the first command in the command buffer.

9. The circuit arrangement of claim 1, wherein the control logic is configured to accumulate commands into a fixed size block and perform the collective operation to store the accumulated commands in the push buffer only after substantially filling the fixed size block.

10. The circuit arrangement of claim 9, wherein the control logic is configured to selectively terminate the accumulation of commands into the fixed size block prior to substantially filling the fixed size block in response to receiving a predetermined command requiring immediate attention by the host interface processor.

11. An integrated circuit device including the circuit arrangement of claim 1.

12. A program product comprising a non-transitory computer readable medium and logic definition program code resident on the computer readable medium and defining the circuit arrangement of claim 1.

3. The circuit arrangement 1, further comprising a plurality of processing cores coupled to one another via a network on chip architecture, wherein the target device comprises a graphics processing unit (GPU) implemented using a first portion of the plurality of processing cores and the host device comprises a central processing unit (CPU) implemented using a second portion of the plurality of processing cores, and wherein the GPU comprises a multithreaded software pipeline controlled by the host interface processor in response to commands from the host device.

13. A circuit arrangement, comprising:

a push buffer configured to store pending commands to be processed by a target device;

a host interface processor disposed in the target device and configured to retrieve pending commands from the push buffer and initiate processing of the commands by the target device;

a command buffer configured to store parameter data associated with a first command;

Direct Memory Access (DMA) logic configured to write the parameter data for the first command in the command buffer; and

control logic configured to store the first command in the push buffer by storing in the push buffer along with the first command a pointer to the parameter data in the command buffer.

14. The circuit arrangement of claim 13, wherein the control logic is further configured to accumulate a plurality of commands from the host device and perform a collective operation to store the accumulated plurality of commands in the push buffer.

15. The circuit arrangement of claim 14, wherein the control logic is configured to accumulate the plurality of commands in a block, and wherein the control logic includes second Direct Memory Access (DMA) logic configured to write the block of accumulated plurality of commands to the push buffer.

16. The circuit arrangement of claim 14, wherein the control logic is configured to update a pointer in the push buffer after storing the accumulated plurality of commands in the push buffer to notify the host interface processor of the addition of the plurality of commands to the push buffer.

17. The circuit arrangement of claim 14, wherein the control logic is configured to accumulate commands into a fixed size block and perform the collective operation to store the accumulated commands in the push buffer only after substantially filling the fixed size block.

18. The circuit arrangement of claim 17, wherein the control logic is configured to selectively terminate the accumulation of commands into the fixed size block prior to substantially filling the fixed size block in response to receiving a predetermined command requiring immediate attention by the host interface processor.

19. A method of passing commands from a host device to a target device via a push buffer interposed therebetween, the method comprising:

accumulating a plurality of commands from the host device;

after accumulating the plurality of commands, performing a collective operation to store the accumulated plurality of commands in the push buffer; and

with a host interface processor disposed in the target device, retrieving commands from the push buffer and initiating processing of the commands by the target device.

20. The method of claim 19, wherein accumulating the plurality of commands includes accumulating the plurality of commands in a block, and wherein performing the collective operation includes using Direct Memory Access (DMA) logic to write the block of accumulated plurality of commands to the push buffer.

21. The method of claim 19, further comprising updating a pointer in the push buffer after storing the accumulated plurality of commands in the push buffer to notify the host interface processor of the addition of the plurality of commands to the push buffer.

22. The method of claim 19, further comprising:

storing parameter data for a first command from among the accumulated plurality of commands in a command buffer; and

storing, along with the first command in the push buffer, a pointer to the parameter data in the command buffer.

23. The method of claim 19, wherein accumulating the plurality of commands includes accumulating commands into a fixed size block, and wherein performing the collective operation to store the accumulated commands in the push buffer is performed only after substantially filling the fixed size block.

24. The method of claim 23, further comprising selectively terminating the accumulation of commands into the fixed size block prior to substantially filling the fixed size block in response to receiving a predetermined command requiring immediate attention by the host interface processor.

25. A method of passing commands from a host device to a target device via a push buffer interposed therebetween, the method comprising:

with Direct Memory Access (DMA) logic, writing parameter data for a first command in a command buffer;

storing the first command in the push buffer, including storing in the push buffer along with the first command a pointer to the parameter data in the command buffer; and

with a host interface processor disposed in the target device, retrieving the first command from the push buffer and initiating processing of the first command by the target device.