Providing Silicon Integrated Code For A System

• US 20110320798A1
• Filed: 06/25/2010
• Published: 12/29/2011
• Est. Priority Date: 06/25/2010
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Zimmer, Vincent J., Xing, Bin, Robinson, Scott H.
• Granted Patent: US 8,522,066 B2
• Time in Patent Office: Days
• US Class Current: 713/2
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/1092 Rebuilding, e.g. when physically replacing a failing disk
• CPC Class Codes: G06F 21/14 against software analysis or reverse engineering, e.g. by obfuscation
• CPC Class Codes: G06F 21/572 Secure firmware programming, e.g. of basic input output system [BIOS]
• CPC Class Codes: G06F 21/575 Secure boot
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57

Abstract

In one embodiment, a semiconductor integrated code (SIC) may be provided in a binary format by a processor manufacturer. This SIC may include platform independent code of the processor manufacturer. Such code may include embedded processor logic to initialize the processor and at least one link that couples the processor to a memory, and embedded memory logic to initialize the memory. Other embodiments are described and claimed.

Claims

1. An apparatus comprising:

a non-volatile storage to store semiconductor integrated code (SIC) corresponding to platform independent code of a processor manufacturer, the SIC including an embedded processor logic to initialize a processor and at least one link that couples the processor to a memory, and an embedded memory logic to initialize the memory, wherein the SIC is to be executed responsive to a processor reset and prior to providing control to pre-boot code of an original equipment manufacturer (OEM).

2. The apparatus of claim 1, further comprising an initial program loader (IPL) to load the SIC, the IPL to be launched from microcode of the processor, wherein the IPL is to authenticate the SIC and then to launch the SIC.

3. The apparatus of claim 2, wherein the IPL is to access a firmware interface table (FIT) having an entry including a pointer to point to a location of the SIC.

4. The apparatus of claim 3, wherein the SIC is provided as a binary to the OEM for inclusion in the non-volatile storage, the non-volatile storage including OEM basic input/output system (BIOS).

5. The apparatus of claim 4, wherein the non-volatile storage includes a plurality of SIC revisions, each associated with a corresponding SIC data module, and wherein the IPL is to select one of the plurality of SIC versions and SIC data modules to launch based on entries in the FIT.

6. The apparatus of claim 5, wherein the SIC data module includes processor manufacturer data, OEM data, and end user data, wherein the OEM data and the end user data is platform dependent.

7. The apparatus of claim 6, wherein the OEM data is trusted data that is signed by the processor manufacturer prior to insertion into the non-volatile storage.

8. The apparatus of claim 1, wherein the non-volatile storage is of a processor package including a plurality of cores, at least one microcode store, and an integrated memory controller.

9. The apparatus of claim 1, wherein the SIC is to sequester a portion of the memory for the processor, wherein the sequestered portion is to be invisible to an operating system.

10. The apparatus of claim 9, wherein the processor is to store a binary translator in the sequestered portion.

11. A method comprising:

receiving an indication in a system that at least one component is to be dynamically incorporated into the system;

triggering a power management operation via operating system power management (OSPM) code responsive to the indication;

invoking semiconductor integrated code (SIC) from the OSPM code and without entry into a system management mode, the SIC corresponding to platform independent code of a processor manufacturer, and executing initialization of the at least one component using the SIC; and

unloading the SIC and returning to the OSPM, wherein the SIC is provided as a binary module by the processor manufacturer to an original equipment manufacturer (OEM) of the system.

12. The method of claim 11, further comprising accessing a SIC data module using the SIC, based on an entry in a firmware interface table (FIT).

13. The method of claim 12, further comprising executing the initialization using information in the SIC data module.

14. The method of claim 11, further comprising launching the SIC to perform initialization of a processor and memory of the system on system startup.

15. The method of claim 14, further comprising after performing the initialization, storing the SIC in a sequestered portion of the memory setup by the SIC.

16. The method of claim 15, further comprising invoking the SIC stored in the sequestered portion.

17. The method of claim 11, further comprising synthesizing a peripheral device address in a chipset and invoking the SIC via an access to the peripheral device address by the OSPM code.

18. A system comprising:

a processor including a plurality of cores and a non-volatile memory, the non-volatile memory to semiconductor integrated code (SIC) corresponding to platform independent code of a manufacturer of the processor, the SIC including an embedded processor logic to initialize the processor and at least one link that couples the processor to a system memory, and an embedded memory logic to initialize the system memory, wherein the SIC is to be executed responsive to a processor reset and prior to providing control to an original equipment manufacturer (OEM) basic input/output system (BIOS);

a flash memory to store firmware of the OEM, the firmware including the OEM BIOS; and

the system memory coupled to the processor.

19. The system of claim 18, further comprising an initial program loader (IPL) to authenticate and then launch the SIC, the IPL to be launched from microcode of the processor.

20. The system of claim 19, wherein the SIC is to sequester a portion of the system memory for exclusive use by the processor during system operation, wherein the sequestered portion is to be invisible to an operating system.