SWITCH FAILOVER CONTROL IN A MULTIPROCESSOR COMPUTER SYSTEM

• US 20110320861A1
• Filed: 06/23/2010
• Published: 12/29/2011
• Est. Priority Date: 06/23/2010
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Craddock, David F., Gregg, Thomas A., Jung, Michael, Kohler, Andreas, Szwed, Peter K., Bayer, Gerd K., Nass, Elke G., Schlag, Oliver G.
• Granted Patent: US 8,677,180 B2
• Time in Patent Office: Days
• US Class Current: 714/5.11
• CPC Class Codes: G06F 11/2033 switching over of hardware resources
• CPC Class Codes: G06F 11/2038 with a single idle spare processing component
• CPC Class Codes: G06F 11/2043 where the redundant components share a common memory address space

Abstract

A system and a method for failover control comprising: maintaining a primary device table entry (DTE) in a first table activated for a first adapter in communication with a first processor node having a first root complex via a first switch assembly and maintaining a secondary DTE in standby for a second adapter in communication with a second processor node having a second root complex via a second switch assembly; maintaining a primary DTE in a second table activated for the second adapter and maintaining a secondary DTE in standby for the first adapter; and upon a failover, updating the secondary DTE in the first table as an active entry for the second adapter and forming a path to enable traffic to route from the second adapter through the second switch assembly over to the first switch assembly and up to the first root complex of the first processor node.

Claims

1. A computer implemented method for failover control in a computer system, the method comprising:

maintaining a primary device table entry (DTE) in a first device table activated for a first adapter in communication with a first host processor node having a first root complex via a first switch assembly and maintaining a secondary DTE in standby for a second adapter in communication with a second host processor node having a second root complex via a second switch assembly;

maintaining a primary DTE in a second device table activated for the second adapter and maintaining a secondary DTE in standby for the first adapter; and

upon a failover condition, updating the secondary DTE in the first device table as an active entry for the second adapter and forming a failover path to enable traffic to route from the second adapter through the second switch assembly over to the first switch assembly and up to the first root complex of the first host processor node.

2. The method of claim 1, wherein each DTE for each adapter enables each host processor node to communicate to each adapter.

3. The method of claim 1, wherein each DTE for each adapter in each device table includes error state information, address translation protection information, interrupt information or a combination thereof.

4. The method of claim 1, further comprising maintaining a third device table accessible by each of the first and second host processor nodes, the third device table includes function table entries that identify to a processor in each of the first and second host processor nodes routing information for communicating to each of the first and second adapters.

5. The method of claim 4, further comprising updating the third device table in response to the failover condition to identify a new routing path for the first host processor node to take to communicate to the second adapter.

6. The method of claim 1, wherein forming the failover path comprises reconfiguring an upstream-facing bridge in the first switch assembly to operate as a down-stream facing failover bridge and reconfiguring a downstream-facing bridge in the second switch assembly to operate as an upstream-facing failover bridge.

7. The method of claim 1, further comprising resetting a first bit in the second adapter to stop the second adapter from generating new requests to the first and second host processor nodes.

8. The method of claim 1, wherein the first processor node is in signal communication with the second processor node via a single symmetric multi-processor bus.

9. A computer system for failover control, comprising:

a first host processor node with a first root complex in communication with a first adapter via a first switch assembly;

a second host processor node with a second root complex in communication with a second adapter via a second switch assembly;

a first device table in the first host processor node, the first device table includes a primary device table entry (DTE) activated for the first adapter and a secondary DTE in standby for the second adapter; and

a second device table in the second host processor node, the second device table includes a primary (DTE) activated for the second adapter and a secondary DTE in standby for the first adapter;

wherein the computing system has a failover condition, in which the secondary DTE in the first device table is updated as an active entry for the second adapter, and in which a failover path is formed and traffic is routed from the second adapter through the second switch assembly over to the first switch assembly and up to the first root complex of the first host processor node.

10. The computer system of claim 9, wherein each DTE for each adapter enables each host processor node to communicate to each adapter.

11. The computer system of claim 9, wherein each DTE for each adapter in each device table includes error state information, address translation protection information, interrupt information or a combination thereof.

12. The computer system of claim 9, further comprising a third device table in system memory accessible by each of the first and second host processor node, the third device table includes function table entries that identify to a processor in each of the first and second host processor nodes routing information for communicating to each of the first and second adapters.

13. The computer system of claim 12, wherein the third device table is updated in response to the failover condition to identify a new routing path for the first host processor node to take to communicate to the second adapter.

14. The computer system of claim 9, wherein the failover path is formed by reconfiguring an upstream-facing bridge in the first switch assembly to operate as a downstream-facing failover bridge and reconfiguring a downstream-facing bridge in the second switch assembly to operate as an upstream-facing failover bridge.

15. The computer system of claim 9, wherein the first and second adapter includes a first bit each selectively set to stop the adapter from generating new requests to either host processor nodes.

16. The computer system of claim 9, wherein the first processor node is in signal communication with the second processor node via a single symmetric multi-processor bus.

17. A computer program product for failover control in a computer system, the computer program product comprising:

a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising;

maintaining a primary device table entry (DTE) in a first device table activated for a first adapter in communication with a first host processor node having a first root complex via a first switch assembly and maintaining a secondary DTE in standby for a second adapter in communication with a second host processor node having a second root complex via a second switch assembly;

maintaining a primary DTE in a second device table activated for the second adapter and maintaining a secondary DTE in standby for the first adapter; and

upon a failover condition, updating the secondary DTE in the first device table as an active entry for the second adapter and forming a failover path to enable traffic to route from the second adapter through the second switch assembly over to the first switch assembly and up to the first root complex of the first host processor node.

18. The computer program product of claim 17, wherein each DTE for each adapter enables each host processor node to communicate to each adapter.

19. The computer program product of claim 17, wherein each DTE for each adapter in each device table includes error state information, address translation protection information, interrupt information or a combination thereof.

20. The computer program product of claim 17, wherein the method further comprises maintaining a third device table accessible by each of the first and second host processor nodes, the third device table includes function table entries that identify to a processor in each of the first and second host processor nodes routing information for communicating to each of the first and second adapters.

21. The computer program product of claim 20, wherein the method further comprises updating the third device table in response to the failover condition to identify a new routing path for the first host processor node to take to communicate to the second adapter.

22. The computer program product of claim 17, wherein the method of forming the failover path comprises reconfiguring an upstream-facing bridge in the first switch assembly to operate as a down-stream facing failover bridge and reconfiguring a downstream-facing bridge in the second switch assembly to operate as an upstream-facing failover bridge.

23. The computer program product of claim 17, wherein the method further comprises resetting a first bit in the second adapter to stop the second adapter from generating new requests to the first and second host processor nodes.

24. The computer program product of claim 17, wherein the first processor node is in signal communication with the second processor node via a single symmetric multi-processor bus.