Computer System and Method of Protection for the System's Marking Store
First Claim
1. A method for protection of a computer system'"'"'s marking store, comprising the steps of executing a plurality of reading and writing processor operations for data processing by a computer system having a plurality of core processors and a marking store for a memory controller with hardware and firmware control, includingwriting in a processor operation of a processor of computer system to said computer system'"'"'s marking store with a slow Error Correcting Code (ECC) decoder, andcontinuing during said processor operations said data processing, and reading marking store data with a read operationsaid computer system'"'"'s marking store with a fast ECC decoder said computer system'"'"'s marking store with a fast ECC decoder during said data processing by said processor operations, andnotifying said memory controller firmware control when the computer system'"'"'s marking store has been updated to lock writing to the computer system'"'"'s marking store until controller firmware has read any updates of the computer system'"'"'s marking store during said data processing of said processor operations.
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Abstract
A method and apparatus for controlling marking store updates in a central electronic complex with a plurality of core processors and eDRAM cache and interconnect bus to a service processor for loading memory controller firmware to dual-channel DDR3 memory controllers with an internal marking store. Loaded firmware of the memory controllers is responsible for tracking of ECC errors using a ECC decoder control whereby said marking store is written by a slow ECC decoder, and read by a fast ECC decoder for every read operation of said memory controllers to provide a blocking mechanism for notifying marking store firmware when the marking store has been updated and which guarantees that marking store firmware cannot write to the marking store until the marking store firmware has seen updates without causing the marking store hardware to time out.
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Citations
20 Claims
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1. A method for protection of a computer system'"'"'s marking store, comprising the steps of executing a plurality of reading and writing processor operations for data processing by a computer system having a plurality of core processors and a marking store for a memory controller with hardware and firmware control, including
writing in a processor operation of a processor of computer system to said computer system'"'"'s marking store with a slow Error Correcting Code (ECC) decoder, and continuing during said processor operations said data processing, and reading marking store data with a read operation said computer system'"'"'s marking store with a fast ECC decoder said computer system'"'"'s marking store with a fast ECC decoder during said data processing by said processor operations, and notifying said memory controller firmware control when the computer system'"'"'s marking store has been updated to lock writing to the computer system'"'"'s marking store until controller firmware has read any updates of the computer system'"'"'s marking store during said data processing of said processor operations.
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11. A computer system, comprising:
a Central Electronic Complex (CEC) having a plurality of core processors for said computer system which are coupled by an L3 eDRAM cache and interconnect bus of said CEC to a service processor for loading memory controller firmware to dual-channel DDR3 memory controllers with an internal marking store, said CEC having SMP Links and Remote SMP Links for connection of the core processors to other system elements, each of said dual-channel DDR3 memory controllers with loaded firmware having a 4-byte/rank mark store protected by one sense parity bit for marking data associated with each memory rank which is read and written by firmware through scan communication, said loaded firmware of said memory controllers being responsible for tracking of ECC errors using a ECC decoder control whereby said marking store is written by a slow ECC decoder, and read by a fast ECC decoder for every read operation of said memory controllers to provide a blocking mechanism for notifying marking store firmware when the marking store has been updated and which guarantees that marking store firmware cannot write to the marking store until the marking store firmware has seen updates without causing the marking store hardware to time out. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A method of controlling marking store updates in a central electronic complex, comprising the steps of
updating a marking store making an entry with a mark data value generated by an Error Correcting Code (ECC) slow decoder when said ECC slow decoder has found a valid mark and notifying marking store firmware that said marking store has been updated, using said updated mark data value to correct data currently being processed by said ECC slow decoder but not marking a mark store entry associated with a memory rank being decoded that has not been updated, continuing to use the existing mark data associated with said memory rank for data correction for future read operations to said memory rank.
Specification