ONE-TRANSISTOR PIXEL ARRAY WITH CASCODED COLUMN CIRCUIT

• US 20120001236A1
• Filed: 06/30/2011
• Published: 01/05/2012
• Est. Priority Date: 06/30/2010
• Status: Active Grant

• Current Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Original Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Inventors: Fife, Keith
• Granted Patent: US 8,455,927 B2
• Time in Patent Office: Days
• US Class Current: 257/253
• CPC Class Codes: C12Q 1/6869 Methods for sequencing
• CPC Class Codes: G01J 1/46 using a capacitor
• CPC Class Codes: G01N 27/4143 Air gap between gate and channel, i.e. suspended gate [SG] FETs work function measurement per se G01N27/002
• CPC Class Codes: G01N 27/4145 specially adapted for biomolecules, e.g. gate electrode with immobilised receptors
• CPC Class Codes: G01N 27/4148 Integrated circuits therefor, e.g. fabricated by CMOS processing CMOS processing per se H01L21/82
• CPC Class Codes: G01N 33/00 Investigating or analysing materials by specific methods not covered by groups G01N1/00 - G01N31/00
• CPC Class Codes: G01R 29/26 Measuring noise figure; Measuring signal-to-noise ratio
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 29/66 Types of semiconductor device ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: Y10T 436/25875 Gaseous sample or with change of physical state

Abstract

To reduce the pixel size to the smallest dimensions and simplest form of operation, a pixel may be formed by using only one ion sensitive field-effect transistor (ISFET). This one-transistor, or 1T, pixel can provide gain by converting the drain current to voltage in the column. Configurable pixels can be created to allow both common source read out as well as source follower read out. A plurality of the 1T pixels may form an array, having a number of rows and a number of columns and a column readout circuit in each column. A cascoded device enabled during readout may be used to provide increased programmable gain.

Claims

1. A pixel array, comprising:

a plurality of pixels, wherein each pixel comprises;

one and only one chemically-sensitive field-effect transistor (ChemFET), having a floating gate, and a source coupled to a fixed voltage line; and

a cascoded device, coupled to the drain of the ChemFET;

wherein the cascoded device is configured to counteract a gate-to-drain parasitic capacitance of the ChemFET.

2. The pixel array of claim 1, wherein the cascoded device comprises a second transistor that is not a ChemFET.

3. The pixel array of claim 2, wherein the second transistor has a gate coupled to a bias voltage, a source coupled to the drain of the ChemFET, and a drain coupled to a fixed voltage line via a current source.

4. The pixel array of claim 3, wherein the drain of the second transistor is coupled to an output line.

5. The pixel array of claim 1, wherein each ChemFET is an ion sensitive transistor.

6. The pixel array of claim 1, wherein each ChemFET is an NMOS transistor.

7. The pixel array of claim 1, wherein each ChemFET is a PMOS transistor.

8. The pixel array of claim 2, wherein the second transistor is an NMOS transistor.

9. The pixel array of claim 2, wherein the second transistor is a PMOS transistor.

10. The pixel array of claim 1, wherein the cascoded device is a row selection device.

11. A pixel array, comprising:

a plurality of pixels, wherein each pixel comprises;

one and only one chemically-sensitive field-effect transistor (ChemFET), having a floating gate, and a source coupled to a fixed voltage line; and

a cascoded device coupled to the pixel array,

wherein the cascoded device is configured to control the gain of the ChemFET.

12. The pixel array of claim 11, wherein the cascoded device comprises a non-ChemFET transistor having gate coupled to a bias voltage line, a source coupled to the drain of the ChemFET at an end of a column in the pixel array, and a drain coupled to a fixed voltage line via a current source.

13. The pixel array of claim 12, wherein the drain of the cascoded device is coupled to an output line.

14. The pixel array of claim 11, wherein each ChemFET is an ion sensitive transistor.

15. The pixel array of claim 11, wherein the ChemFET is an NMOS transistor.

16. The pixel array of claim 11, wherein the ChemFET is a PMOS transistor.

17. The pixel array of claim 12, wherein the cascoded device is an NMOS transistor.

18. The pixel array of claim 12, wherein the cascoded device is a PMOS transistor.

19. The pixel array of claim 11, wherein the cascoded device is a row selection device.

20. The pixel array of claim 11, wherein the gain of the pixel is programmable by adjusting a load of a current source.

21. The pixel array of claim 11, wherein the plurality of ChemFETs comprise multiple pairs of ChemFETs, and wherein each pair of ChemFETs share a common drain.

22. The pixel array of claim 11, wherein the plurality of ChemFETs comprise multiple pairs of ChemFETs, and wherein each pair of ChemFETs share a common source.

23. The pixel array of claim 11, wherein the cascoded device is gain-enhanced with a differential amplifier in feedback to control a transistor that maintains a constant voltage on the column line.