ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF

• US 20120001252A1
• Filed: 06/30/2010
• Published: 01/05/2012
• Est. Priority Date: 06/30/2010
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Alsmeier, Johann, Purayath, Vinod Robert, Chien, Henry, Matamis, George, Lee, Yao-Sheng, Kai, James, Zhang, Yuan
• Granted Patent: US 8,187,936 B2
• Time in Patent Office: Days
• US Class Current: 257/321
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels

Abstract

Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.

Claims

1. A method of making a monolithic three dimensional NAND string, comprising:

forming a stack of alternating layers of a first material and a second material over a substrate, wherein the first material comprises a conductive or semiconductor control gate material and wherein the second material comprises an insulating material;

etching the stack to form at least one opening in the stack;

selectively etching the first material to form first recesses in the first material;

forming a blocking dielectric in the first recesses;

forming a plurality of discrete charge storage segments separated from each other in the first recesses over the blocking dielectric;

forming a tunnel dielectric over a side wall of the discrete charge storage segments exposed in the at least one opening; and

forming a semiconductor channel in the at least one opening.

2. The method of claim 1, wherein the semiconductor channel has a circular cross section when viewed from above.

3. The method of claim 1, wherein the step of forming the semiconductor channel in the at least one opening completely fills the at least one opening with a semiconductor channel material.

4. The method of claim 1, wherein the step of forming the semiconductor channel in the at least one opening forms a semiconductor channel material on the side wall of the at least one opening but not in a central part of the at least one opening such that the semiconductor channel material does not completely fill the at least one opening.

5. The method of claim 4, further comprising forming an insulating fill material in the central part of the at least one opening to completely fill the at least one opening.

6. The method of claim 1, furthering comprising forming an upper electrode over the semiconductor channel.

7. The method of claim 6, furthering comprising providing a lower electrode below the semiconductor channel prior to forming the stack of alternating layers.

8. The method of claim 1, wherein the step of forming semiconductor channel in the at least one opening comprises:

forming a amorphous semiconductor layer in the at least one opening and over the stack of the alternating layers;

forming an nucleation promoter layer over the amorphous semiconductor layer;

recrystallizing the amorphous semiconductor to form polycrystalline semiconductor layer; and

removing the nucleation promoter layer and an upper portion of the polycrystalline semiconductor layer using top surface of the stack of alternating layers as a stop.

9. The method of claim 8, wherein the nucleation promoter layer comprises at least one of Ge, Ni, Pd, Al or a combination thereof.

10. The method of claim 1, wherein the plurality of discrete charge storage segments comprise a plurality of discrete charge storage dielectric features.

11. The method of claim 1, wherein the plurality of discrete charge storage segments comprise a plurality of floating gates.

12. The method of claim 11, wherein the step of forming the plurality of discrete charge storage segments comprises:

forming a floating gate layer in the first recesses over the blocking dielectric and over a side wall of the at least one opening; and

etching an outer portion of the floating gate layer to leave the plurality of the floating gates in the recesses between overhanging second material layer portions.

13. The method of claim 12, wherein the floating gate layer comprises a semiconductor floating gate material.

14. The method of claim 13, wherein the semiconductor floating gate material comprises polysilicon.

15. The method of claim 13, wherein the step of etching the outer portion of the floating gate layer comprises:

oxidizing the outer portion of the floating gate layer; and

selectively etching the oxidized outer portion of the floating gate layer while leaving unoxidized semiconductor inner portions of the floating gate layer unetched.

16. The method of claim 1, wherein the step of forming the polarity of discrete charge storage segments and forming a tunnel dielectric comprises:

forming a semiconductor layer in the first recesses over the blocking dielectric and over a side wall of the at least one opening; and

oxidizing an outer portion of the semiconductor layer to form the tunnel dielectric, wherein the unoxidized inner portions of the semiconductor layer forms the plurality of the discrete charge storage segments separated from each other in the recesses between overhanging second material layer portions.

17. The method of claim 13, wherein the step of etching the outer portion of the floating gate layer comprises:

converting the outer portion of the floating gate layer to metal silicide; and

selectively etching the metal silicide outer portion of the floating gate layer while leaving unsilicided semiconductor inner portions of the floating gate layer unetched.

18. The method of claim 17, wherein the metal silicide is selected from a group consisting of titanium silicide, cobalt silicide, nickel silicide, molybdenum silicide, or a combination thereof.

19. The method of claim 1, wherein:

the step of forming the blocking dielectric in the first recesses comprises forming a plurality of clam-shaped blocking dielectric segments in the first recesses between overhanging portions of the second material; and

the step of forming the plurality of discrete charge storage segments comprises forming each of the plurality of discrete charge storage segments inside an opening in a respective one of the plurality of clam-shaped blocking dielectric segments.

20. A method of making a monolithic three dimensional NAND string, comprising:

forming at least one sacrificial feature over a substrate;

forming a stack of alternating layers of a first material and a second material over the at least one sacrificial feature, wherein the first material comprises a conductive or semiconductor control gate material and wherein the second material comprises an insulating material;

etching the stack to form at least two openings in the stack;

selectively etching the first material to form first recesses in the first material such that at least some of the first recesses are exposed in a first opening and at least some additional first recesses are exposed in a second opening;

forming a blocking dielectric in the first recesses;

forming a plurality of discrete charge storage segments separated from each other in the first recesses over the blocking dielectric layer;

removing the at least one sacrificial feature to form a hollow region extending substantially parallel to a major surface of the substrate which connects the at least two openings to form a hollow U-shaped pipe space comprising the first and the second openings extending substantially perpendicular to the major surface of the substrate connected by the hollow region;

forming a tunnel dielectric over a side wall of the plurality of discrete charge storage segments exposed in the at least two openings; and

forming a semiconductor channel in the hollow U-shaped pipe space.

21. The method of claim 20, wherein the semiconductor channel has a cross section of two circles when viewed from above.

22. The method of claim 20, wherein the step of forming the semiconductor channel on the side wall of the hollow U-shaped pipe space completely fills the hollow U-shaped pipe space with the semiconductor channel material.

23. The method of claim 20, wherein the step of forming the semiconductor channel in the hollow U-shaped pipe space forms a semiconductor channel material on the side wall of the hollow U-shaped pipe space but not in a central part of the hollow U-shaped pipe space such that the semiconductor channel material does not completely fill the hollow U-shaped pipe space.

24. The method of claim 23, further comprising forming an insulating fill material in the central part of the semiconductor channel to completely fill the hollow U-shaped pipe space.

25. The method of claim 20, furthering comprising forming a source electrode contacting the semiconductor channel located in the first opening and forming a drain electrode contacting the semiconductor channel in the second opening.

26. The method of claim 25, furthering comprising providing a body contact electrode below the stack of alternating layers, wherein the body contact electrode contacts a portion of the semiconductor channel located in the hollow region.

27. A monolithic three dimensional NAND string, comprising:

a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate;

a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level;

a blocking dielectric, the blocking dielectric comprising a plurality of blocking dielectric segments, wherein each of the plurality of blocking dielectric segments is located in contact with a respective one of the plurality of control gate electrodes, and wherein at least a portion of each of the plurality of blocking dielectric segments has a clam shape;

a plurality of discrete charge storage segments, wherein each of the plurality of discrete charge storage segments is located at least partially in a respective clam-shaped blocking dielectric segment, and wherein the plurality of discrete charge storage segments comprise at least a first discrete charge storage segment located in the first device level and a second discrete charge storage segment located in the second device level; and

a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.

28. The monolithic three dimensional NAND string of claim 27, wherein the tunnel dielectric have a not straight sidewall near the plurality of discrete charge storage segments.

29. The monolithic three dimensional NAND string of claim 27, wherein the tunnel dielectric have a non-uniform thickness.

30. The monolithic three dimensional NAND string of claim 27, wherein the plurality of discrete charge storage segments comprise a plurality of floating gates.

31. The monolithic three dimensional NAND string of claim 27, wherein the plurality of discrete charge storage segments comprise a plurality of discrete charge storage dielectric features.

32. The monolithic three dimensional NAND string of claim 31, wherein:

the discrete charge storage dielectric features comprise silicon nitride; and

the blocking dielectric segments and tunnel dielectric comprise silicon oxide.

33. The monolithic three dimensional NAND string of claim 27, wherein:

the semiconductor channel has a pillar shape; and

the entire pillar-shaped semiconductor channel extends substantially perpendicularly to the major surface of the substrate.

34. The monolithic three dimensional NAND string of claim 33, further comprising one of a source or drain electrode which contacts the pillar-shaped semiconductor channel from above, and another one of a source or drain electrode which contacts the pillar-shaped semiconductor channel from below.

35. The monolithic three dimensional NAND string of claim 27, wherein:

the semiconductor channel has U-shaped pipe shape; and

two wing portions of the U-shaped pipe shape semiconductor channel extend substantially perpendicular to the major surface of the substrate and a connecting portion of the U-shaped pipe shape semiconductor channel which connects the two wing portions extends substantially perpendicular to the major surface of the substrate.

36. The monolithic three dimensional NAND string of claim 35, further comprising one of a source or drain electrode contacts the first wing portion of the semiconductor channel from above, and another one of a source or drain electrode which contacts the second wing portion of the semiconductor channel from above.

37. The monolithic three dimensional NAND string of claim 35, further comprising a body contact electrode which contacts the connecting portion of the semiconductor channel from below.