ETCHANTS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES USING THE SAME

• US 20120001264A1
• Filed: 06/30/2011
• Published: 01/05/2012
• Est. Priority Date: 07/02/2010
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Hwang, Ki-hyun, Ahn, Jae-Young, Yang, Jun-kyu, Kim, Hong-suk, Kim, Jin-gyun, Lim, Hun-Hyeong
• Application Number:
  US13/173,360
• Publication Number:
  US 20120001264A1
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: C09K 13/04 containing an inorganic acid
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Provided according to embodiments of the present invention are methods of fabricating semiconductor devices using an etchant. In some embodiments, the etchant may be highly selective and may act to reduce interference between wordlines in the semiconductor device. In some embodiments of the invention, provided are methods of fabricating a semiconductor device that include forming a plurality of gate patterns on a substrate; forming first insulation layers between the gate patterns; wet-etching the first insulation layers to form first insulation layer residues; and forming air gaps between the plurality of gate patterns. Related etchant solutions and semiconductor devices are also provided.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

forming a plurality of gate patterns on a substrate;

forming first insulation layers between the gate patterns;

wet-etching the first insulation layers to form first insulation residues; and

forming air gaps between the plurality of gate patterns.

2. The method of claim 1, wherein the wet-etching is performed using an etchant comprising phosphoric acid (H₃PO₄) and silicon phosphate (Si₃(PO₄)₄).

3. The method of claim 2, wherein the concentration of Si in the etchant is from about 10 to about 1000 ppm with respect to the total weight of the etchant solution.

4. The method of claim 1, wherein the air gaps are formed between the substrate and the first insulation residues.

5. The method of claim 1, further comprising forming a second insulation layer on the substrate and on the gate patterns before forming the first insulation layers,

wherein the first insulation layers are selectively etched over the second insulation layer.

6. The method of claim 1, further comprising heating the first insulation residues to form third insulation layers.

7. The method of claim 6, wherein the third insulation layers have an etching selectivity different from that of the first insulation layers.

8. The method of claim 6, wherein the third insulation layers are on the gate patterns.

9. The method of claim 8, wherein the third insulation layers on the gate patterns contact each other.

10. The method of claim 8, wherein the third insulation layers on the gate patterns do not contact each other, so that there are slits between adjacent third insulation layers.

11. The method of claim 10, further comprising forming a fourth insulation layer on the third insulation layers that covers the slits between adjacent third insulation layers.

12. A method of fabricating a semiconductor device, the method comprising:

forming a plurality of gate patterns on a substrate;

forming a first oxide layer on the substrate and on the gate patterns;

forming nitride layers between the gate patterns;

forming a residue of the nitride layers by etching the nitride layers using an etchant comprising phosphoric acid (H₃PO₄) and silicon phosphate (Si₃(PO₄)₄); and

forming second oxide layers by heating the residue,

wherein air gaps are formed between the plurality of gate patterns.

13. The method of claim 12, wherein the concentration of Si in the etchant is from about 10 to about 1000 ppm with respect to the total weight of the etchant solution.

14. The method of claim 12, wherein the nitride layers are wet-etched at a temperature in a range of from about 25°

C. to about 200°

C. for a time period in a range from about 5 minutes to about 30 minutes.

15. The method of claim 12, wherein the second oxide layers are formed on the gate patterns.

16. The method of claim 15, wherein the second oxide layers formed on the gate patterns contact each other.

17. The method of claim 15, wherein the second oxide layers formed on the gate patterns do not contact each other, so that there are slits between adjacent second oxide layers.

18. The method of claim 17, further comprising forming a third oxide layer on the second oxide layers that covers the slits between adjacent second oxide layers.

19. An etchant comprising phosphoric acid (H₃PO₄) and silicon phosphate (Si₃(PO₄)₄).

20. The etchant of claim 19, wherein the concentration of Si in the etchant is from about 10 to about 1000 ppm with respect to the total weight of the etchant solution.

21-23. -23. (canceled)

24. A semiconductor device comprising

a plurality of gate patterns;

and

a silicon dioxide layer on the plurality of gate patterns; and

air gaps enclosed by the gate patterns and the silicon dioxide layer thereon.