GALVANIC ISOLATION TRANSFORMER

• US 20120002377A1
• Filed: 06/30/2010
• Published: 01/05/2012
• Est. Priority Date: 06/30/2010
• Status: Abandoned Application

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: French, William, Hopper, Peter J., Smeys, Peter, Gabrys, Ann, Anderson, David I.
• Application Number:
  US12/827,316
• Publication Number:
  US 20120002377A1
• Time in Patent Office: Days
• US Class Current: 361/748
• CPC Class Codes: H01F 2019/085 Transformer for galvanic isolation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/12043 Photo diode
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15747 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: Y10T 29/49128 Assembling formed circuit to base

Abstract

An integrated circuit die system comprises a first integrated circuit die, a second integrated circuit die and a transformer formed on a dielectric (e.g., quartz) substrate and electrically connected between the first integrated circuit die and the second integrated circuit die to provide galvanic isolation therebetween.

Claims

1. An integrated circuit system comprising:

a first integrated circuit die having a first integrated circuit formed thereon;

a second integrated circuit die having a second integrated circuit formed thereon; and

a transformer formed on a dielectric substrate and electrically connected between the first integrated circuit and the second integrated circuit.

2. The integrated circuit system of claim 1, wherein the dielectric substrate comprises a quartz substrate.

3. The integrated circuit system of claim 1, wherein the dielectric substrate comprises a glass substrate

4. The integrated circuit system of claim 1, wherein the transformer comprises an air core transformer.

5. The integrated circuit system as in claim 1, wherein the transformer includes a magnetic core.

6. The integrated circuit system of claim 1, wherein the first integrated circuit die and the second integrated circuit die are attached to the dielectric substrate.

7. The integrated circuit system of claim 1, wherein the first integrated circuit has a voltage of greater than or equal to 5 kV associated therewith.

8. An integrated circuit system comprising:

a quartz substrate;

a first integrated circuit die attached to the quartz substrate and having a first integrated circuit formed thereon, the first integrated circuit having a first voltage associated therewith;

a second integrated circuit die attached to the quartz substrate and having a second integrated circuit formed thereon, the second integrated circuit having a second voltage associated therewith, the second voltage being less than the first voltage; and

a transformer system formed on the quartz substrate and electrically connected between the first integrated circuit and the second integrated circuit to provide galvanic isolation therebetween.

9. The integrated circuit system of claim 8, wherein the first integrated circuit die and the second integrated circuit die are formed on the quartz substrate.

10. The integrated circuit system of claim 8, wherein the first voltage is greater than or equal to 5 kV.

11. The integrate circuit system of claim 8, wherein the transformer system comprises an inter-wound transformer.

12. The integrated circuit system of claim 8, wherein the transformer system comprises a stacked transformer.

13. The integrated circuit system of claim 8, wherein the transformer system comprises multiple inter-wound transformers to provide multi-channel signal communication between the first integrated circuit and the second integrated circuit.

14. The integrated circuit system of claim 8, wherein

the first integrated circuit includes a first encoder/decoder that encodes data generated by the first integrated circuit and transmits the encoded data to the second integrated circuit via the transformer, and wherein

the second integrated circuit includes a second encoder/decoder that decodes the encoded data transmitted by the first integrated circuit and extracts the data for utilization by the second integrated circuit.

20. The method of claim 12, wherein the transformer system comprises multiple inter-wound transformers to provide multi-channel signal communication between the first integrated circuit and the second integrated circuit.

15. A method of forming an integrated circuit system comprising:

providing a first integrated circuit die having a first integrated circuit formed thereon;

providing a second integrated circuit die having a second integrated circuit formed thereon; and

electrically connecting a transformer system formed on a dielectric substrate between the first integrated circuit and the second integrated circuit to provide galvanic isolation therebetween.

16. The method of claim 15, wherein the dielectric substrate comprises quartz.

17. The method of claim 15, wherein the first integrated circuit die system and the second integrated circuit die system are attached to the quartz substrate.

18. The method of claim 15, wherein the transformer system comprises an inter-wound transformer.

19. The method of claim 15, wherein the transformer system comprises a stacked transformer.