SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME

• US 20120003828A1
• Filed: 06/30/2011
• Published: 01/05/2012
• Est. Priority Date: 07/01/2010
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Chang, Sung-Il, Kang, Changseok, Choe, Byeong-In
• Application Number:
  US13/173,321
• Publication Number:
  US 20120003828A1
• Time in Patent Office: Days
• US Class Current: 438/591
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A method of manufacturing a semiconductor device includes forming a laminated structure including sacrificial layers and a select gate layer on a substrate, forming a penetration region penetrating the laminated structure, forming a select gate insulating layer on a sidewall of the select gate layer exposed by the penetration region, and forming an active pattern in the penetration region. The method also includes exposing a portion of the active pattern by removing the sacrificial layers and forming an information storage layer on the exposed portion of the active pattern.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

forming a laminated structure including sacrificial layers and a select gate layer on a substrate;

forming a penetration region penetrating the laminated structure;

forming a select gate insulating layer on a sidewall of the select gate layer exposed by the penetration region;

forming an active pattern in the penetration region;

exposing a portion of the active pattern by removing the sacrificial layers; and

forming an information storage layer on the exposed portion of the active pattern.

2. The method as claimed in claim 1, wherein:

the select gate insulating layer is formed before the active pattern is formed, and

the information storage layer is formed after the active pattern is formed.

3. The method as claimed in claim 1, wherein the select gate layer is formed of polysilicon.

4. The method as claimed in claim 1, wherein forming the select gate insulating layer includes performing a thermal oxidation process.

5. The method as claimed in claim 1, further comprising, after forming the information storage layer, forming cell gate layers that fill spaces in the laminated structure formed by the removing of the sacrificial layers.

6. The method as claimed in claim 1, wherein forming the select gate layer of the laminated structure includes:

forming a lower select gate layer between the sacrificial layers and the substrate, and

forming an upper select gate layer on the sacrificial layers.

7. The method as claimed in claim 1, further comprising forming a buffer insulating layer on the substrate before forming the laminated structure such that the buffer layer is between the substrate and the laminated structure.

8. The method as claimed in claim 7, wherein forming the penetration region includes exposing the buffer insulating layer,

further comprising exposing the substrate by removing the buffer insulating layer exposed by the penetration region after forming the select gate insulating layer.

9. The method as claimed in claim 7, wherein:

forming the penetration region includes penetrating the buffer insulating layer to expose the substrate, and

after forming the select gate insulating layer by a thermal oxidation process, removing a substrate thermal oxide layer formed on the exposed substrate.

10. The method as claimed in claim 1, further comprising, before forming the select gate insulating layer, recessing a sidewall of the select gate layer exposed by the penetration region.

11. A method of manufacturing a three-dimensional semiconductor memory device, the method comprising:

forming a laminated structure including sacrificial layers and a select gate layer such that the sacrificial layers and the select gate layer are stacked in a first direction;

forming a penetration region penetrating the laminated structure such that the penetration region extends through the sacrificial layers and the select gate layer in the first direction;

forming a select gate insulating layer on a sidewall of the select gate layer exposed by the penetration region, the sidewall of the select gate layer extending in the first direction;

forming an active pattern in the penetration region such that the active pattern extends through the sacrificial layers and the select gate layer in the first direction;

exposing a portion of the active pattern by removing the sacrificial layers; and

forming an information storage layer on the exposed portion of the active pattern.

12. The method as claimed in claim 11, wherein:

removing the sacrificial layers includes forming a trench extending in the first direction through the laminated structure such that the sacrificial layers are exposed by the trench, and the trench is spaced apart from the penetration region, and

the information storage layer is formed in recesses exposed by the trench after removing the sacrificial layers.

13. The method as claimed in claim 12, wherein forming the information storage layer includes sequentially forming a tunnel insulating layer, a charge storage layer, and a blocking layer in the recesses after removing the sacrificial layers.

14. The method as claimed in claim 12, further comprising, after forming the information storage layer, forming a gate conductive layer in recesses remaining after forming the information storage layer, wherein

the gate conductive layer is formed of a first material and the select gate is formed of a second material, the first material being different from the second material.

15. The method as claimed in claim 12, wherein:

the information storage layer is formed through the trench on sidewalls of the recesses, and

a gate conductive layer is formed through the trench to completely fill the recesses such that the information storage layer surrounds the gate conductive layer in the recesses.

16-20. -20. (canceled)