Memory Controller for Controlling Write Signaling

• US 20120005437A1
• Filed: 09/12/2011
• Published: 01/05/2012
• Est. Priority Date: 10/10/1997
• Status: Active Grant

• Current Assignee: Abhijit M. Abhyankar, Craig E. Hampel, David Q. Nguyen, Donald C. Stark, Frederick A. Ware, James A. Gasbarro, Paul G. Davis, Richard M. Barth
• Original Assignee: Abhijit M. Abhyankar, Craig E. Hampel, David Q. Nguyen, Donald C. Stark, Frederick A. Ware, James A. Gasbarro, Paul G. Davis, Richard M. Barth
• Inventors: Barth, Richard M., Ware, Frederick A., Stark, Donald C., Hampel, Craig E., Davis, Paul G., Abhyankar, Abhijit M., Gasbarro, James A., Nguyen, David
• Granted Patent: US 8,205,056 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/2218 Late write
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A memory controller has an interface to convey, over a first set of interconnect resources: a first command that specifies activation of a row of memory cells, a second command that specifies a write operation directed to the row of memory cells, a bit that specifies whether precharging will occur in connection with the write operation, a code that specifies whether data mask information will be issued in connection with the write operation, and if the code specifies that data mask information will be issued, data mask information that specifies whether to selectively write portions of write data associated with the write operation. The memory controller interface further conveys, over a second set of interconnect resources, separate from the first set of interconnect resource, the write data.

Claims

1. A memory controller having an interface to convey:

over a first set of interconnect resources;

a first command that specifies activation of a row of memory cells;

a second command that specifies a write operation directed to the row of memory cells;

a bit that specifies whether precharging will occur in connection with the write operation;

a code that specifies whether data mask information will be issued in connection with the write operation; and

if the code specifies that data mask information will be issued, data mask information that specifies whether to selectively write portions of write data associated with the write operation; and

over a second set of interconnect resources, separate from the first set of interconnect resource, the write data.

2. The memory controller of claim 1, wherein two consecutive bits of the data mask information are conveyed during a clock cycle of a clock signal that is received by the memory device.

3. The memory controller of claim 1, wherein the first set of interconnect resources conveys a column address that identifies a subset of memory cells in the row.

4. The memory controller of claim 3, wherein the interface conveys, over the first set of interconnect resources:

a first bank address that is associated with the first command, the first bank address to identify a bank of a plurality of memory cell banks in which to perform the activation; and

a second bank address that is associated with the second command and the column address, wherein the second command specifies the write operation to be performed in a bank identified by the second bank address.

5. The memory controller of claim 4, wherein:

the interface conveys the first command and first bank address to a first portion of the first set of interconnect resources; and

the interface conveys the second command, second bank address, column address, bit, and code, to a second portion of the first set of interconnect resources.

6. The memory controller of claim 5, wherein:

the first command and first bank address are conveyed in a first packet to the first set of interconnect resources; and

the second command, second bank address, column address, bit, and code are conveyed in a second packet to the first set of interconnect resources.

7. The memory controller of claim 6, wherein:

the first portion of the first set of interconnect resources is a primary interconnect consisting of three signal lines;

the second portion of the first set of interconnect resources is a secondary interconnect consisting of five signal lines; and

the second set of interconnect resources is a data bus consisting of eighteen signal lines.

8. A memory controller for controlling a memory device, comprising:

a first interface portion to convey;

a first command and a first bank address to activate a row in a bank identified by the first bank address;

a second command and a second bank address, the second command specifying a write operation;

a code that specifies whether data mask information will be issued in connection with the write operation; and

if the data mask information will be issued in connection with the write operation, data mask information that specifies whether to selectively write portions of the write data, in connection with the write operation, to a bank identified by the second bank address; and

a second interface portion to convey the write data.

9. The memory controller of claim 8, wherein the first interface portion:

conveys the first command and first bank address in a first packet; and

conveys the second command and code in a second packet.

10. The memory controller of claim 9, wherein:

the first packet is conveyed by the first interface portion to a primary interconnect consisting of three signal lines; and

the second packet is conveyed by the first interface portion to a secondary interconnect consisting of five signal lines.

11. The memory controller of claim 8, wherein the first interface portion conveys a column address that identifies a column associated with the write operation and conveys both a bit of the second bank address and a bit of the column address over a common signal line during a clock cycle of a clock signal that is received by the memory device.

12. The memory controller of claim 11, the code and a first bit are conveyed synchronously with respect to a first transition of the clock signal, wherein the first bit specifies whether precharging occurs in connection with writing the write data.

13. The memory controller of claim 12, wherein the column address and the data mask information are conveyed synchronously with respect to transitions of the clock signal which succeed the first transition of the clock signal.

14. The memory controller of claim 8, wherein the first interface portion conveys, to at least a first signal line, two consecutive bits of the data mask information during a clock cycle of a clock signal that is received by the memory device.

15. The memory controller of claim 8, wherein the first interface portion conveys a column address that identifies a column associated with the write operation, wherein the first bank address and the second bank address identify the same bank of the plurality of banks, such that the column address identifies a column of the row activated in the same bank identified by both the first and second bank address.

16. The memory controller of claim 8, wherein the first bank address identifies a first bank of the plurality of banks and the second bank address identifies a second bank of the plurality of banks, wherein the first bank and second bank are different banks.

17. The memory controller of claim 8, wherein, the first interface portion:

conveys the first command and first bank address to a first external interconnect; and

conveys the second command, second bank address, and code, to a second external interconnect that is separate from the first external interconnect.

18. A memory controller for controlling a memory device, comprising:

an interface to convey;

a first command that specifies activation of a row of memory cells; and

a second command that specifies a write operation; and

write data over a set of interconnect resources that are separate from interconnect resources used to convey the first command and the second command;

wherein the interface conveys, to a first interconnect resource;

a code that specifies whether data mask information will be issued in connection with the write operation, wherein the code is conveyed synchronously with respect to a first transition of a clock signal that is received by the memory device; and

if the code specifies that the data mask information will be issued, two bits of the data mask information during a clock cycle of the clock signal, wherein if the data mask information is conveyed, the data mask information specifies whether to selectively write portions of the write data to the row of memory cells in connection with the write operation.

19. The memory controller of claim 18, wherein the interface conveys, to a second interconnect resource, precharge information synchronously with respect to the first transition of the clock signal, wherein the precharge information specifies whether precharging occurs after the write data is written.

20. The memory controller of claim 18, wherein the interface conveys column address information associated with the write operation, wherein the column address information identifies a subset of memory cells in the row.

21. The memory controller of claim 20, wherein:

the interface conveys, to a second interconnect resource, precharge information synchronously with respect to the first transition of the clock signal;

the precharge information specifies whether precharging occurs after the write data is written; and

the interface conveys a portion of the column address information synchronously with respect to a transition of the clock signal that succeeds the first transition of the clock signal.