ADAPTIVE EVENT-GUIDED SYSTEM AND METHOD FOR AVOIDING VOLTAGE EMERGENCIES

• US 20120005515A1
• Filed: 02/11/2010
• Published: 01/05/2012
• Est. Priority Date: 02/12/2009
• Status: Active Grant

• Current Assignee: President and Fellows of Harvard College (Harvard Corporation)
• Original Assignee: President and Fellows of Harvard College (Harvard Corporation)
• Inventors: Wei, Gu-Yeon, Smith, Michael D., Brooks, David, Reddi, Vijay Janapa, Gupta, Meeta Sharma, Holloway, Glenn
• Granted Patent: US 8,949,666 B2
• Time in Patent Office: Days
• US Class Current: 713/340
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision

Abstract

In a preferred embodiment, the present invention is a system for avoiding voltage emergencies. The system comprises a microprocessor, an actuator for throttling the microprocessor, a voltage emergency detector and a voltage emergency predictor. The voltage emergency detector may comprise, for example, a checkpoint recovery mechanism or a sensor. The voltage emergency predictor of a preferred embodiment comprises means for tracking control flow instructions and microarchitectural events, means for storing voltage emergency signatures that cause voltage emergencies, means for comparing current control flow and microarchitectural events with stored voltage emergency signatures to predict voltage emergencies, and means for actuating said actuator to throttle said microprocessor to avoid predicted voltage emergencies.

Claims

1. A system for avoiding voltage emergencies comprising:

a microprocessor;

an actuator for throttling said microprocessor;

a voltage emergency detector; and

a voltage emergency predictor comprising;

means for tracking control flow instructions and microarchitectural events;

means for storing voltage emergency signatures corresponding to voltage emergencies detected by said voltage emergency detector;

means for comparing current control flow and microarchitectural events with stored voltage emergency signatures to predict voltage emergencies;

means for actuating said actuator to throttle said microprocessor to avoid predicted voltage emergencies.

2. A system for avoiding voltage emergencies according to claim 1, wherein said emergency detector comprises a checkpoint recovery mechanism.

3. A system for avoiding voltage emergencies according to claim 1, wherein said emergency detector comprises a sensor.

4. A system for avoiding voltage emergencies according to claim 3, further comprising:

a checkpoint recovery mechanism for recovering the system and resuming execution after voltage emergencies.

5. A system for avoiding voltage emergencies comprising:

a microprocessor;

an actuator for throttling said microprocessor;

a sensor for detecting voltage emergencies;

a checkpoint recovery mechanism for recovery and resumption of execution after a voltage emergency occurs; and

a voltage emergency predictor comprising;

means for tracking control flow instructions and microarchitectural events;

means for storing voltage emergency signatures corresponding to voltage emergencies detected by said voltage emergency detector;

means for comparing current control flow and microarchitectural events with stored voltage emergency signatures to predict voltage emergencies;

means for actuating said actuator to throttle said microprocessor to avoid predicted voltage emergencies.

6. A method for preventing voltage emergencies in a microprocessor comprising the steps of:

tracking control flow instructions and microarchitectural events in said microprocessor;

identifying voltage emergencies that occur in said microprocessor;

storing voltage emergency signatures corresponding to identified voltage emergencies;

comparing current control flow and microarchitectural events in said microprocessor with stored voltage emergency signatures to predict impending voltage emergencies; and

throttling said microprocessor to avoid said impending voltage emergencies.

7. A method for preventing voltage emergencies in a microprocessor according to claim 6, wherein said step of identifying voltage emergencies comprises detecting execution errors in said microprocessor with a checkpoint recovery mechanism.

8. A method for preventing voltage emergencies in a microprocessor according to claim 7 wherein said step of identifying voltage emergencies further comprises recovery and resumption of execution with said checkpoint recovery mechanism.

9. A method for preventing voltage emergencies in a microprocessor according to claim 6, wherein said step of identifying voltage emergencies comprises detecting a voltage surpassing a threshold.

10. A method for preventing voltage emergencies in a microprocessor according to claim 9 wherein said step of identifying voltage emergencies further comprises recovery and resumption of execution with a checkpoint recovery mechanism.