MEMORY SYSTEM AND COMMAND HANDLING METHOD

• US 20120005555A1
• Filed: 09/09/2011
• Published: 01/05/2012
• Est. Priority Date: 02/08/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LEE, Jung-Bae
• Granted Patent: US 8,205,135 B2
• Time in Patent Office: Days
• US Class Current: 714/758
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence

Abstract

A memory system including a memory controller and a memory and a related method are disclosed. The method includes communicating a command and error detection/correction (EDC) data associated with the command from the memory controller to the memory, decoding the command and executing an EDC operation related to the EDC data in parallel, and if the command is a write command, delaying execution of a write operation indicated by the write command until completion of the EDC operation, else immediately executing an operation indicated by the command without regard to completion of the EDC operation.

Claims

1. A memory, comprising:

a memory core;

a receiver block that receives a command indicating an operation and error detection/correction (EDC) data, and in response, generates an internal command, internal EDC data, and an internal address;

a decoding/execution block that decodes the command in parallel with beginning execution of an EDC operation using the EDC data, immediately executes the operation without regard to completion of the EDC operation unless the command is a write command, but delays execution of the operation if the command is a write command until completion of the EDC operation, wherein the decoding/execution block comprises;

an error decoder that receives the internal EDC data, the internal command and the internal address and in response generates an error signal;

a command decoder that receives the internal command and in response generates a plurality of control signals including a write enable signal; and

a write signal transfer block that receives the write enable signal and the error signal and in response generates a final write enable signal applied to the memory core to execute a write operation.

2. The memory of claim 1, wherein the receiver block comprises a packet receiver and the command is a command packet.

3. The memory of claim 2, wherein the command packet comprises at least one of control data, address data and write data.

4. The memory of claim 3, wherein the command packet further comprises the EDC data.

5. The memory of claim 1, wherein the command and the EDC data are communicated to the receiver block via a channel connecting the memory with an external circuit.

6. The memory of claim 5, wherein the channel comprises a first unidirectional bus communicating the command and the EDC data from the external circuit to the memory.

7. The memory of claim 6, wherein the channel further comprises a second unidirectional bus communicating read data from the memory to the external circuit.

8. The memory of claim 7, wherein the first and second unidirectional buses have different bus widths.

9. The memory of claim 5, wherein the channel comprises a bidirectional bus communicating write data and read data between the memory and the external circuit.

10. The memory of claim 5, wherein the external circuit is a memory controller.

12. The memory of claim 2, wherein the command packet comprises a first command packet including control data, address data, and first EDC data associated with at least one of the control data and the address data, and a second command packet including write data and second EDC data associated with the write data, and

the packet receiver receives the first command packet, and in response, generates the internal command, the internal address, first internal EDC data, and a first packet indicating signal.

13. The memory of claim 12, wherein the error decoder receives the first internal EDC data, the internal command, the internal address, and the first packet indicating signal, and in response, generates a first error signal, and

the write signal transfer block receives the write enable signal and the first error signal, and in response, generates the final write enable signal.

14. The memory of claim 13, wherein the first command packet and the second command packet are communicated to the packet receiver via a first unidirectional bus of a channel connecting the memory with an external circuit.

15. The memory of claim 14, wherein the channel further comprises a second unidirectional bus communicating read data associated with at least one of the first and second command packets between the memory and the external circuit.

16. The memory of claim 15, wherein the external circuit is a memory controller.

11. The memory of 1, wherein the EDC data is cyclic redundancy checker (CRC) data and the EDC operation is a CRC operation using the CRC data.

17. A flash memory, comprising:

a memory core comprising flash memory cells;

a packet receiver that receives a command packet including a command indicating an operation and error detection/correction (EDC) data, and in response, generates an internal command, internal EDC data, and an internal address;

a decoding/execution block that decodes the command in parallel with beginning execution of an EDC operation using the EDC data, immediately executes the operation without regard to completion of the EDC operation unless the command is a write command, but delays execution of the operation if the command is a write command until completion of the EDC operation, wherein the decoding/execution block comprises;

an error decoder that receives the internal EDC data, the internal command and the internal address and in response generates an error signal;

a command decoder that receives the internal command and in response generates a plurality of control signals including a write enable signal; and

a write signal transfer block that receives the write enable signal and the error signal and in response generates a final write enable signal applied to the memory core to execute a write operation.

18. The flash memory of claim 17, wherein the command is a write command and the command packet further includes address data and write data associated with the write command.

19. The flash memory of claim 17, wherein the command packet is communicated to the packet receiver via a channel connecting the memory with a memory controller.

20. The flash memory of claim 19, wherein the channel comprises a first unidirectional bus communicating the command packet from the memory controller to the memory.

21. The flash memory of claim 20, wherein the channel further comprises a second unidirectional bus communicating read data from the memory to the external circuit.

22. The flash memory of claim 21, wherein the first and second unidirectional buses have different bus widths.