SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND IC CARD MOUNTING SAME

• US 20120006905A1
• Filed: 03/31/2010
• Published: 01/12/2012
• Est. Priority Date: 04/15/2009
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Watanabe, Kazuki, Toriyama, Akihiro
• Granted Patent: US 8,403,233 B2
• Time in Patent Office: Days
• US Class Current: 235/492
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: H04B 5/26 using coils
• CPC Class Codes: H04B 5/72 for local intradevice communication
• CPC Class Codes: H04B 5/79 for data transfer in combination with power transfer

Abstract

In an IC card, even in the case where an undershoot or an overshoot which occurs at the time of an amplitude change by communication data is large, the amplitude change is accurately detected.

A semiconductor integrated circuit device B2 has antenna terminals LA and LB, a power supply circuit B3 for generating power supply voltage from an alternating-current (AC) signal supplied to the antenna terminals, and a receiver circuit B5 for demodulating an information signal which is superimposed on the AC signal. The receiver circuit B5 includes a rectifier circuit B9, a filter circuit B10, a capacitor C1, an amplifier A1, a feedback path B11, a switch circuit SW1, a binarizing circuit B12, and a control circuit B13. An output signal S3 of the amplifier A1 is transmitted to an inverting input terminal—of A1 via B11 and SW1, and the switch circuit SW1 is controlled by an output signal SC1 of the control circuit B13. In a lapse period of predetermined time T1 since level changes X and Y of an output signal SR of the binarizing circuit B12, the switch circuit SW1 is controlled to an off state by the output signal SC1 of the control circuit B13.

Claims

1. A semiconductor integrated circuit device comprising:

an antenna terminal coupled to an antenna;

a power supply circuit that generates power supply voltage from an alternating-current (AC) signal supplied from the antenna to the antenna terminal; and

a receiver circuit that demodulates an information signal which is superimposed on the AC signal,

wherein the receiver circuit comprises a rectifier circuit, a filter circuit, a capacitor, an amplifier, a feedback path, a switch circuit, a binarizing circuit, and a control circuit,

wherein the rectifier circuit rectifies the AC signal supplied to the antenna terminal to smooth the AC signal,

wherein the filter circuit is configured for an output signal of the rectifier circuit to be supplied to an input terminal of the filter circuit which reduces a high frequency component,

wherein the amplifier is configured for an output signal of the filter circuit to be supplied to an inverting input terminal of the amplifier via the capacitor,

wherein the amplifier has a function of inverting and amplifying an input signal supplied to the inverting input terminal with respect to a first reference voltage,

wherein the inverting input terminal is configured for an output signal of the amplifier to be transmitted to the inverting input terminal via the feedback path and the switch circuit,

wherein the switch circuit is configured to be controlled by an output signal of the control circuit,

wherein the binarizing circuit binarizes the output signal of the amplifier, and

wherein, in a lapse period of predetermined time since a level change in an output signal of the binarizing circuit, the switch circuit is controlled to an off state by the output signal of the control circuit.

2. The semiconductor integrated circuit device according to claim 1,

wherein, when the switch circuit is controlled to the off state in the lapse period of the predetermined time, the feedback path is electrically separated from at least any of the inverting input terminal of the amplifier and an output terminal for generating the output signal.

3. The semiconductor integrated circuit device according to claim 2,

wherein the feedback path comprises two diode elements which are coupled in opposite directions.

4. The semiconductor integrated circuit device according to claim 2, further comprising:

a voltage drop element that generates a voltage drop between the inverting input terminal of the amplifier and the output terminal for generating the output signal.

5. The semiconductor integrated circuit device according to claim 2,

wherein the control circuit is configured for a control signal to be supplied to the control circuit, and the lapse period of the predetermined time is variably set by the control signal.

6. The semiconductor integrated circuit device according to claim 2,

wherein the receiver circuit further comprises a determining circuit,

wherein the determining circuit determines communication speed of the information signal superimposed on the AC signal from the output signal of the binarizing circuit,

wherein the control signal as a result of determination of the determining circuit is supplied from the determining circuit to the control circuit, and in response to the control signal, the lapse period of the predetermined time is variably set.

7. The semiconductor integrated circuit device according to claim 3,

wherein the diode element of the feedback path comprises a diode of p-n junction.

8. The semiconductor integrated circuit device according to claim 3,

wherein the diode element of the feedback path comprises a P-channel MOS transistor and an N-channel MOS transistor.

9. The semiconductor integrated circuit device according to claim 4,

wherein the voltage drop element of the feedback path comprises a resistor.

10. The semiconductor integrated circuit device according to claim 1,

wherein the amplifier is an operational amplifier, and the first reference voltage is supplied to a non-inverting input terminal of the operational amplifier.

11. An IC card mounted with a semiconductor integrated circuit device and an antenna over a main surface of a substrate, the antenna being formed by a wire,

wherein the semiconductor integrated circuit device comprises:

an antenna terminal coupled to an antenna;

a power supply circuit that generates power supply voltage from an alternating-current (AC) signal supplied from the antenna to the antenna terminal; and

a receiver circuit that demodulates an information signal which is superimposed on the AC signal,

wherein the receiver circuit comprises a rectifier circuit, a filter circuit, a capacitor, an amplifier, a feedback path, a switch circuit, a binarizing circuit, and a control circuit,

wherein the rectifier circuit rectifies the AC signal supplied to the antenna terminal to smooth the AC signal,

wherein the filter circuit is configured for an output signal of the rectifier circuit to be supplied to an input terminal of the filter circuit which reduces a high frequency component,

wherein the amplifier is configured for an output signal of the filter circuit to be supplied to an inverting input terminal of the amplifier via the capacitor,

wherein the amplifier has a function of inverting and amplifying an input signal supplied to the inverting input terminal with respect to a first reference voltage,

wherein the inverting input terminal is configured for an output signal of the amplifier to be transmitted to the inverting input terminal via the feedback path and the switch circuit,

wherein the switch circuit is configured to be controlled by an output signal of the control circuit,

wherein the binarizing circuit binarizes the output signal of the amplifier, and

wherein in a lapse period of predetermined time since a change in level of an output signal of the binarizing circuit, the switch circuit is controlled to an off state by the output signal of the control circuit.

12. The IC card according to claim 11,

wherein, when the switch circuit is controlled to the off state in the lapse period of the predetermined time, the feedback path is electrically separated from at least any of the inverting input terminal of the amplifier and an output terminal for generating the output signal.

13. The IC card according to claim 12,

wherein the feedback path comprises two diode elements which are coupled in opposite directions.

14. The IC card according to claim 12, further comprising:

a voltage drop element that generates a voltage drop between the inverting input terminal of the amplifier and the output terminal for generating the output signal.

15. The IC card according to claim 12,

wherein the control circuit is configured for a control signal to be supplied to the control circuit, and the lapse period of the predetermined time is variably set by the control signal.

16. The IC card according to claim 12,

wherein the receiver circuit further comprises a determining circuit,

wherein the determining circuit determines communication speed of the information signal superimposed on the AC signal from the output signal of the binarizing circuit,

wherein the control signal as a result of determination of the determining circuit is supplied from the determining circuit to the control circuit, and in response to the control signal, the lapse period of the predetermined time is variably set.

17. The IC card according to claim 13,

wherein the diode element of the feedback path comprises a diode of p-n junction.

18. The IC card according to claim 13,

wherein the diode element of the feedback path comprises a P-channel MOS transistor and an N-channel MOS transistor.

19. The IC card according to claim 14,

wherein the voltage drop element of the feedback path comprises a resistor.

20. The IC card according to claim 11,

wherein the amplifier is an operational amplifier, and the first reference voltage is supplied to a non-inverting input terminal of the operational amplifier.