NON-VOLATILE MEMORY TRANSISTOR HAVING DOUBLE GATE STRUCTURE

• US 20120007158A1
• Filed: 06/30/2011
• Published: 01/12/2012
• Est. Priority Date: 07/12/2010
• Status: Abandoned Application

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: YOON, Sung Min, Yang, Shin Hyuk, Byun, Chun Won, Ryu, Min Ki, Jung, Soon Won
• Application Number:
  US13/173,625
• Publication Number:
  US 20120007158A1
• Time in Patent Office: Days
• US Class Current: 257/295
• CPC Class Codes: H01L 29/22 including, apart from doping materials or other impurities, only AIIBVI compounds
• CPC Class Codes: H01L 29/40111 the electrodes comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H01L 29/516 with at least one ferroelectric layer
• CPC Class Codes: H01L 29/78391 the gate comprising a layer which is used for its ferroelectric properties

Abstract

Provided is a non-volatile memory transistor having a double gate structure, including a first gate electrode formed on a substrate and to which an operating voltage is applied, a first gate insulating layer formed on the first gate electrode, source and drain electrodes formed on the first gate insulating layer at predetermined intervals, a channel layer formed on the first gate insulating layer between the source and drain electrodes, a second gate insulating layer formed on the channel layer, and a second gate electrode formed on the second gate insulating layer and connected to the first gate electrode such that the operating voltage is applied thereto. Accordingly, a turn-on voltage of the memory transistor can be easily controlled.

Claims

1. A non-volatile memory transistor having a double gate structure, comprising:

a first gate electrode formed on a substrate and to which an operating voltage is applied;

a first gate insulating layer formed on the first gate electrode;

source and drain electrodes formed on the first gate insulating layer at predetermined intervals;

a channel layer formed on the first gate insulating layer between the source and drain electrodes;

a second gate insulating layer formed on the channel layer; and

a second gate electrode formed on the second gate insulating layer and connected to the first gate electrode such that the operating voltage is applied thereto.

2. The transistor of claim 1, wherein, during an on-write operation, a positive write voltage is applied to the first and second gate electrodes.

3. The transistor of claim 1, wherein, during an off-write operation, a negative write voltage is applied to the first and second gate electrodes.

9. The transistor of claim 1, wherein the channel layer is formed of an oxide semiconductor, which is transparent in a visible wavelength range.

11. The transistor of claim 1, wherein the second gate insulating layer is formed of an organic ferroelectric.

12. The transistor of claim 1, further comprising a passivation layer formed on the channel layer.

13. The transistor of claim 1, wherein the channel layer covers sidewalls and parts of top surfaces of the source and drain electrodes.

14. The transistor of claim 1, wherein the source and drain electrodes cover sidewalls and a part of a top surface of the channel layer.

4. A non-volatile memory transistor having a double gate structure, comprising:

a first gate electrode formed on a substrate and to which a control voltage for controlling a turn-on voltage of the transistor is applied;

a first gate insulating layer formed on the first gate electrode;

source and drain electrodes formed on the first gate insulating layer at predetermined intervals;

a channel layer formed on the first gate insulating layer between the source and drain electrodes;

a second gate insulating layer formed on the channel layer; and

a second gate electrode formed on the second gate insulating layer and to which an operating voltage is applied when the control voltage is applied to the first gate electrode.

5. The transistor of claim 4, wherein the control voltage having a negative value is applied to the first gate electrode, and the non-volatile memory transistor has a positive turn-on voltage.

6. The transistor of claim 4, wherein, during an on-write operation, a positive write voltage is applied to the second gate electrode when a negative control voltage is applied to the first gate electrode.

7. The transistor of claim 4, wherein, during an off-write operation, a negative write voltage is applied to the second gate electrode when a negative control voltage is applied to the first gate electrode.

8. The transistor of claim 4, wherein, during a read operation, a read voltage is applied to the second gate electrode when a negative control voltage is applied to the first gate electrode.

10. The transistor of claim 4, wherein the channel layer is formed of an oxide semiconductor, which is transparent in a visible wavelength range.

15. The transistor of claim 4, wherein the channel layer is formed of an oxide semiconductor, which is transparent in a visible wavelength range.

16. The transistor of claim 4, wherein the second gate insulating layer is formed of an organic ferroelectric.

17. The transistor of claim 4, further comprising a passivation layer formed on the channel layer.

18. The transistor of claim 4, wherein the channel layer covers sidewalls and parts of top surfaces of the source and drain electrodes.

19. The transistor of claim 4, wherein the source and drain electrodes cover sidewalls and a part of a top surface of the channel layer.