Multi-gate Transistor Having Sidewall Contacts

• US 20120007183A1
• Filed: 07/08/2010
• Published: 01/12/2012
• Est. Priority Date: 07/08/2010
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Chang, Josephine B., Guo, Dechao, Han, Shu-Jen, Lin, Chung-Hsun
• Granted Patent: US 8,338,256 B2
• Time in Patent Office: Days
• US Class Current: 257/365
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer.

Claims

1. A method for fabricating a FinFET device, the method comprising:

forming a semiconductor fin on a semiconductor substrate, and etching a trench within the semiconductor fin;

depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench;

forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer;

removing exposed portions of the dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer;

forming a high-k material liner along sidewalls of the channel region in the semiconductor fin;

forming a metal gate stack within the etched trench; and

forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer.

2. The method of claim 1, wherein the semiconductor fin is formed of silicon.

3. The method of claim 1, wherein the dummy oxide layer is formed of silicon dioxide.

4. The method of claim 1, wherein the spacer dielectric layer is formed of nitride.

5. The method of claim 1, wherein the removing of exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer forms a curved trench within the channel region, wherein the high-k material liner is formed along the curved trench.

6. The method of claim 5, wherein current flows through the channel region in a direction along the high-k material liner to the plurality of sidewall contacts.

7. The method of claim 5, wherein a depth of the curved trench ranges from approximately 2 nanometers (nm) to approximately 5 nanometers (nm).

8. The method of claim 1, wherein the plurality of sidewall contacts are formed of a predetermined thickness ranging from approximately 5 nanometers (nm) to approximately 10 nanometers (nm)

9. The method of claim 1, wherein a predetermined thickness of the exposed trench ranges from approximately 2 nanometers (nm) to approximately 5 nanometers (nm).

10. The method of claim 1, wherein the plurality of sidewall contacts are formed of silicide.

11. A semiconductor fin field-effect-transistor (FinFET) device comprising:

a semiconductor fin formed in a substrate;

a trench formed within the semiconductor fin having a curved surface along a channel region in the semiconductor fin;

a metal gate stack formed within the trench; and

a plurality of sidewall contacts formed along adjacent sidewalls of the metal gate stack.

12. The FinFET device of claim 11, wherein the semiconductor fin is formed of silicon.

13. The FinFET device of claim 11, wherein a dummy oxide layer is formed along exposed sidewall surfaces of the trench.

14. The FinFET device of claim 13, wherein the dummy oxide layer is formed of silicon dioxide.

15. The FinFET device of claim 13, wherein a spacer dielectric layer is formed along vertical sidewall surfaces of the dummy oxide layer.

16. The FinFET of claim 15, wherein the spacer dielectric layer is formed of nitride.

17. The FinFET of claim 11, wherein a high-k material liner is formed along the curved surface of the trench.

18. The FinFET device of claim 17, wherein current flows through the channel region in a direction along the high-k material liner to the plurality of sidewall contacts.

19. The FinFET device of claim 11, wherein a depth of the curved surface ranges from approximately 2 nanometers (nm) to approximately 5 nanometers (nm).

20. The FinFET device of claim 11, wherein the plurality of sidewall contacts are formed of a predetermined thickness ranging from approximately 5 nanometers (nm) to approximately 10 nanometers (nm).

21. The FinFET device of claim 11, wherein a predetermined thickness of the trench ranges from approximately 2 nanometers (nm) to approximately 5 nanometers (nm).

22. The FinFET device of claim 11, wherein the plurality of sidewall contacts are formed of silicide.

23. A multi-gate transistor comprising:

a semiconductor fin formed in a substrate;

a trench formed within the semiconductor fin having a curved surface along a channel region in the semiconductor fin;

a metal gate stack formed within the trench; and

a plurality of sidewall contacts formed along adjacent sidewalls of the metal gate stack.