Multiple Monitor Video Control

• US 20120007875A1
• Filed: 07/12/2010
• Published: 01/12/2012
• Est. Priority Date: 07/12/2010
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Sethuraman, Saravanan, Venkiteswaran, Sreekrishnan
• Application Number:
  US12/834,129
• Publication Number:
  US 20120007875A1
• Time in Patent Office: Days
• US Class Current: 345/545
• CPC Class Codes: G06F 3/1431 using a single graphics controller

Abstract

A computer system comprising a processor including a display controller operative to output display data and a clock signal, and a programmable logic device communicatively connected to the processor, the programmable logic device including a first FIFO (first in first out) module operative to receive display data from the display controller and output display data to a display device, a second FIFO module, a scaler module communicatively connected to the first FIFO module and the second FIFO module operative to scale the display data received from the first FIFO module and output the scaled display data to the second FIFO module, and a synchronization generator operative to receive the clock signal from the display controller and to control the first FIFO and the second FIFO.

Claims

1. A computer system comprising:

a processor including a display controller operative to output display data and a clock signal; and

a programmable logic device communicatively connected to the processor, the programmable logic device including;

a first FIFO (first in first out) module operative to receive display data from the display controller and output display data to a display device;

a second FIFO module;

a scaler module communicatively connected to the first FIFO module and the second FIFO module operative to scale the display data received from the first FIFO module and output the scaled display data to the second FIFO module; and

a synchronization generator operative to receive the clock signal from the display controller and to control the first FIFO and the second FIFO.

2. The system of claim 1, wherein the system further includes a first interface converter communicatively connected to the programmable logic device and the display device, the first interface converter operative to receive display data from the programmable logic device.

3. The system of claim 2, wherein the first interface converter is operative to receive timing signals from the synchronization generator and output the display data to the display device.

4. The system of claim 1, wherein the system further includes a second interface converter communicatively connected to the programmable logic device and a second display device, the second interface converter operative to receive display data from the programmable logic device.

5. The system of claim 4, wherein the second interface converter is operative to receive timing signals from the synchronization generator and output the display data to the second display device.

6. The system of claim 1, wherein the programmable logic device includes a register array operative to store configuration data to control the synchronization generator and the scaler.

7. The system of claim 6, wherein the register array is communicatively connected to the processor.

8. The system of claim 1, wherein the system further includes a switch communicatively connected to the first FIFO and the second FIFO.

9. The system of claim 1, wherein the system further comprises of a first buffer communicatively connected to the switch and to the first interface converter.

10. The system of claim 1, wherein the system further comprises of a second buffer communicatively connected to the switch and to the second interface converter.

11. The system of claim 1, wherein the synchronization generator includes a clock generator operative to receive the clock signal, and output a pulse signal to a first timing generator and a second timing generator.

12. A method for displaying data in a system, the method including:

receiving configuration data from a first display device and a second display device;

comparing the configuration data to identify which display device operates at a higher resolution;

configuring a first set of registers in the system with operating parameters associated with the higher resolution display;

configuring a second set of registers in the system with operating parameters associated with the lower resolution display;

receiving display data at the higher resolution and a pixel clock signal from a processor;

clocking the display data at the higher resolution into a first FIFO module;

scaling the display data from the higher resolution to the lower resolution;

clocking the display data at the lower resolution into a second FIFO module;

switching the display data at the higher resolution to the display device having higher resolution; and

switching the display data at the lower resolution to the display device having lower resolution.

13. The method of claim 12, wherein the first set of registers are associated with a display controller associated with the processor, and the second set of registers are associated with a programmable logic device.

14. The method of claim 12, wherein the display data at the higher resolution is switched from the first FIFO module to the interface converter associated with the higher resolution display device.

15. The method of claim 12, wherein the display data at the lower resolution is switched from the second FIFO module to the interface converter associated with the lower resolution display device

16. The method of claim 12, wherein clocking of the display data from the FIFO modules to the interface converters is synchronized with the respective timing signals generated by the synchronization generator.

17. A system comprising:

a processor operative to receive display data from a memory and output the display data and a pixel clock signal; and

a programmable logic device connected to the processor operative to receive the display data and the pixel clock signal and clock the display data into a first FIFO module, scale the display data from a first resolution into a second resolution, clock the scaled display data in the second resolution into a second FIFO module, switch the display data from the first FIFO module to an interface converter associated with a higher resolution display device, switch the display data from the second FIFO module to an interface converter associated with a lower resolution display device, and output the display data from the interface converters to the associated display devices.

18. The system of claim 17, wherein the processor is operative to receive a signal from the higher resolution display device indicating the resolution of the higher resolution display device.

19. The system of claim 17, wherein the processor is operative to receive a signal from the lower resolution display device indicating the resolution of the lower resolution display device.