NONVOLATILE MEMORY DEVICES, MEMORY SYSTEMS AND METHODS OF PERFORMING READ OPERATIONS

• US 20120008389A1
• Filed: 02/23/2011
• Published: 01/12/2012
• Est. Priority Date: 07/06/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KIM, Seung-Bum
• Granted Patent: US 8,582,365 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

Within a non-volatile memory device, a read operation directed to a nonvolatile memory cell having a positive threshold voltage applies a positive read voltage to a selected word line and a first control signal to a page buffer connected to a selected bit line, but if the memory cell has a negative threshold voltage the read operation applies a negative read voltage to the selected word line and a second control signal to the page buffer different from the first control signal.

Claims

1. A method of operating a non-volatile memory device, comprising:

during a read operation directed to a nonvolatile memory cell having a positive threshold voltage and being connected between a selected word line and a selected bit line, applying a positive read voltage to the selected word line and a first control signal to a page buffer connected to the selected bit line, wherein the first control signal defines a first read operation interval comprising a first discharge interval, a first pre-charge interval, a first developing interval, and a first sensing interval; and

during a read operation directed to the memory cell having a negative threshold voltage, applying a negative read voltage to the selected word line and a second control signal to the page buffer different from the first control signal, wherein the second control signal defines a second read operation interval longer in duration than the first read operation interval and comprising a second discharge interval, a second pre-charge interval, a second developing interval, and a second sensing interval.

2. The method of claim 1, wherein the second control signal causes relatively more electrical charge to be accumulated or retained on the selected bit line than the first control signal.

3. The method of claim 1, wherein the second pre-charge interval is longer in duration than the first pre-charge interval.

4. The method of claim 3, wherein the second read operation interval is longer in duration than the first read operation interval.

5. The method of claim 1, wherein the second pre-charge interval begins relatively sooner in the second read operation interval than the first pre-charge interval begins in the first read operation interval.

6. The method of claim 1, wherein the second developing interval begins relatively later in the second read operation interval than the first developing interval begins in the first read operation interval.

7. The method of claim 1, wherein a first time period over which the positive read voltage is applied to the selected word line and a second time period over which the negative read voltage is applied to the selected word line are symmetrical over at least respective portions of the first and second read operation intervals and with respect to an initial word line voltage.

8. The method of claim 1, wherein a first time period over which the positive read voltage is applied to the selected word line and a second time period over which the negative read voltage is applied to the selected word line are asymmetrical over at least respective portions of the first and second read operation intervals and with respect to an initial word line voltage.

9. The method of claim 8, wherein the second time period is longer than the first time period.

10. The method of claim 8, wherein the negative read voltage is applied to the selected word line in relation to a negative target voltage with a different voltage slope characteristic than the positive read voltage is applied to the selected word line in relation to a positive target voltage.

11. The method of claim 10, wherein a voltage slope characteristic for the negative read voltage is steeper towards the negative target voltage than a voltage slope characteristic for the positive read voltage is towards the positive target voltage.

12. The method of claim 8, wherein an absolute value of a positive difference between the initial word line voltage and a positive target voltage associated with the positive read voltage is less than an absolute value of a negative difference between the initial word line voltage and a negative target voltage associated with the negative read voltage.

13. The method of claim 1, wherein the read operation is a program-read-verify operation, or an erase-read-verify operation.

14. The method of claim 1, wherein the nonvolatile memory cell is a multi-level memory cell (MLC).

15. The method of claim 1, wherein the nonvolatile memory cell is a NAND type flash memory cell.

16. A method of operating a non-volatile memory device, comprising:

during a read operation directed to a memory cell connected between a selected word line and a selected bit line and applying a positive read voltage to the selected word line, applying a bit line voltage to the selected bit line at a first time relative to a time at which the positive read voltage is applied to the selected word line; and

during a read operation directed to the memory cell and applying a negative read voltage to the selected word line, applying the bit line voltage to the selected bit line at a second time later than the first time, such that application of the bit line voltage occurs during an interval wherein the negative read voltage is transitioning from an initial word line voltage to a negative target voltage.

17. The method of claim 16, wherein the memory cell has a threshold voltage between the negative target voltage and the negative read voltage such that an ON period for the memory cell following application of the negative read voltage is reduced.

18. A method of reading data stored in a non-volatile memory cell according to a defined threshold voltage distribution, the memory cell being connected between a selected word line and a selected bit line and the method comprising:

determining whether the threshold voltage distribution is positive or negative;

if the threshold voltage distribution is positive, applying a positive read voltage to the selected word line during a first read operation interval including a first discharge interval, a first pre-charge interval, a first developing interval, and a first sensing interval; and

if the threshold voltage is negative, applying a negative read voltage to the selected word line during a second read operation interval different from the first read operation interval and including a second discharge interval, a second pre-charge interval, a second developing interval, and a second sensing interval.

19. The method of claim 18, wherein the second pre-charge interval is longer than the first pre-charge interval.

20. The method of claim 18, further comprising:

generating a first control signal defining the first read operation interval if the threshold voltage distribution is positive; and

generating a second control signal defining the second read operation interval if the threshold voltage distribution is negative.

21-33. -33. (canceled)