NONVOLATILE MEMORY DEVICE AND METHOD OF ERASING THE SAME

• US 20120008412A1
• Filed: 07/06/2011
• Published: 01/12/2012
• Est. Priority Date: 07/09/2010
• Status: Abandoned Application

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: PARK, Young Soo
• Application Number:
  US13/177,002
• Publication Number:
  US 20120008412A1
• Time in Patent Office: Days
• US Class Current: 365/185.22
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells

Abstract

A method of erasing a nonvolatile memory device includes the steps of supplying an erase voltage to the P well of a semiconductor substrate having a memory cell block disposed therein; performing a first erase verification operation for verifying the erase state of memory cells coupled to the even bit lines of the memory cell block; making a determination of success or failure for the first erase verification operation; and if, as a result of the determination for the first erase verification operation, all the memory cells coupled to the even bit lines are determined to be erased, performing a second erase verification operation for verifying the erase state of memory cells coupled to odd bit lines of the memory cell block.

Claims

1. A method of erasing a nonvolatile memory device, the method comprising the steps of:

supplying an erase voltage to a P well of a semiconductor substrate having a memory cell block disposed therein;

performing a first erase verification operation for verifying an erase state of memory cells coupled to even bit lines of the memory cell block;

making a determination of success or failure for the first erase verification operation; and

if, as a result of the determination for the first erase verification operation, all the memory cells coupled to the even bit lines are determined to be erased, performing a second erase verification operation for verifying an erase state of memory cells coupled to odd bit lines of the memory cell block.

2. The method of claim 1, further comprising the steps of:

if, as a result of the determination for the first erase verification operation, one or more of all the memory cells coupled to the even bit lines are determined not to be erased, raising the erase voltage by a step voltage; and

performing the steps from the step of supplying the erase voltage to the P well by using the raised erase voltage.

3. The method of claim 1, further comprising the steps of:

if, as a result of the determination for the first erase verification operation, one or more of all the memory cells coupled to the odd bit lines are determined not to be erased, raising the erase voltage by a step voltage and supplying the raised erase voltage to the P well; and

performing the steps from the step of performing the second erase verification operation.

4. A method of erasing a nonvolatile memory device, the method comprising the steps of:

supplying an erase voltage to a P well of a semiconductor substrate having a memory cell block disposed therein;

performing an even verification operation for verifying an erase state of memory cells coupled to even bit lines of the memory cell block;

if a result of the even verification operation is determined to be failure, raising the erase voltage by a step voltage and performing the steps from the step of supplying the erase voltage to the P well by using the raised erase voltage;

if the result of the even verification operation is determined to be success, performing an odd verification operation for verifying an erase state of memory cells coupled to odd bit lines of the memory cell block;

if a result of the odd verification operation is determined to be failure, raising the erase voltage by the step voltage, supplying the raised erase voltage to the P well, and performing the odd verification operation again; and

if the result of the odd verification operation is determined to be success, finishing an erase operation.

5. The method of claim 4, wherein if, as a result of the even verification operation, at least one of the memory cells coupled to the even bit lines is determined not to be erased, the failure is determined.

6. The method of claim 4, wherein if, as the result of the odd verification operation, at least one of the memory cells coupled to the odd bit lines is determined not to be erased, the failure is determined.

7. A method of erasing a nonvolatile memory device, the method comprising the steps of:

supplying an erase voltage to a P well of a semiconductor substrate having a memory cell block disposed therein;

performing a first erase verification operation for verifying an erase state of memory cells coupled to even bit lines of the memory cell block;

making a determination of success or failure for the first erase verification operation;

if, as a result of the determination, the first erase verification operation is determined to be the failure, raising the erase voltage by a step voltage and supplying the raised erase voltage to the P well;

performing a second erase verification operation for verifying an erase state of memory cells coupled to odd bit lines of the memory cell block;

making a determination of success or failure for the second erase verification operation; and

if, as a result of the determination, the second erase verification operation is determined to be the failure, raising the erase voltage by the step voltage, supplying the raised erase voltage to the P well, and performing the steps from the step of performing the first erase verification operation.

8. The method of claim 7, further comprising the steps of:

if, as a result of the determination, the first erase verification operation is determined to be the success, performing a third erase verification operation for verifying an erase state of the memory cells coupled to the odd bit lines; and

if a result of the third erase verification operation is determined to be success, an erase operation is finished, and if the result of the third erase verification operation is determined to be failure, raising the erase voltage by the step voltage, supplying the raised erase voltage to the P well, and performing the steps from the step of performing the third erase verification operation.

9. The method of claim 7, further comprising the steps of:

if, as a result of the determination, the second erase verification operation is determined to be the success, performing a fourth erase verification operation for verifying an erase state of the memory cells coupled to the even bit lines; and

if a result of the fourth erase verification operation is determined to be success, an erase operation is finished, and if the result of the fourth erase verification operation is determined to be failure, raising the erase voltage by the step voltage, supplying the raised erase voltage to the P well, and performing the steps from the step of performing the fourth erase verification operation.

10. A nonvolatile memory device, comprising:

a memory cell block configured to comprise a plurality of bit lines having a plurality of memory cells coupled thereto;

a circuit group configured to erase the memory cell block; and

a controller configured to control the circuit group,

wherein the controller controls the circuit group so that the circuit group performs processes of;

supplying an erase voltage to a P well of a semiconductor substrate having the memory cell block disposed therein,

performing a first erase verification operation for verifying an erase state of memory cells, coupled to even bit lines of the plurality of bit lines, by supplying a verification voltage to relevant word lines of the memory cell block,

if a result of the first erase verification operation is determined to be failure, raising the erase voltage by a step voltage and supplying the raised erase voltage to the P well,

performing a second erase verification operation for verifying an erase state of memory cells, coupled to odd bit lines of the plurality of bit lines, and

if a result of the second erase verification operation is determined to be failure, raising the erase voltage by the step voltage, supplying the raised erase voltage to the P well, and performing the processes from the process of performing the first erase verification operation.

11. The nonvolatile memory device of claim 10, wherein the circuit group comprises:

a page buffer unit coupled to the plurality of bit lines and configured to detect verification data for the plurality of memory cells;

a verification unit configured to determine an erase operation for the plurality of memory cells, coupled to the plurality of bit lines, based on the verification data; and

a voltage generator configured to supply the verification voltage to the relevant word lines and supply the erase voltage to the P well.

12. A nonvolatile memory device, comprising:

a memory cell block configured to comprise a plurality of even and odd bit lines having a plurality of memory cells coupled thereto;

a page buffer unit coupled to the plurality of even and odd bit lines and configured to detect verification data of the plurality of memory cells; and

a voltage generator configured to supply a verification voltage to word lines of the memory cell block and supply an erase voltage to a P well of a semiconductor substrate having the memory cell block disposed therein,

wherein after the voltage generator supplies the erase voltage to the P well,

the page buffer unit performs an erase verification operation for memory cells coupled to the even bit lines, from among the plurality of memory cells, and if a result of the erase verification operation is determined to be success, performs the erase verification operation for memory cells coupled to the odd bit lines, from among the plurality of memory cells.

13. The nonvolatile memory device of claim 12, wherein if a result of the erase verification operation for the memory cells coupled to the even bit lines is determined to be failure,

the voltage generator raises the erase voltage by the step voltage and supplies the raised erase voltage to the P well, and

the page buffer unit performs the erase verification operation for the memory cells coupled to the even bit lines again.

14. The nonvolatile memory device of claim 12, wherein if a result of the erase verification operation for the memory cells coupled to the odd bit lines is determined to be failure,

the voltage generator raises the erase voltage by the step voltage and supplies the raised erase voltage to the P well, and

the page buffer unit performs the erase verification operation for the memory cells coupled to the odd bit lines again.