WIDE BAND CLOCK DATA RECOVERY

• US 20120008727A1
• Filed: 07/11/2011
• Published: 01/12/2012
• Est. Priority Date: 07/12/2010
• Status: Active Grant

• Current Assignee: Ensphere Solutions, Inc.
• Original Assignee: Ensphere Solutions, Inc.
• Inventors: Tourette, Bruno, MOHAJERI, Hessam, Afifi, Emad
• Granted Patent: US 8,804,888 B2
• Time in Patent Office: Days
• US Class Current: 375/376
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

The present disclosure provides a clock data recovery circuit that includes a phase locked loop unit, a delay locked loop unit and digital clock data recovery unit. The phase locked loop unit generates a clock signal based on a reference signal. The delay locked loop unit receives the clock signal from the phase locked loop, divides the clock signal into a plurality of clock signals and outputs the clock signals. The digital clock data recovery unit receives an input current signal, estimates a frequency of the input current signal, outputs a reference signal having the frequency, which can be transmitted to the phase locked loop unit, receives the clock signals from the delay locked loop, aligns a phase of the input current signal based on the clock signals and outputs an aligned current signal.

Claims

1. A clock data recovery circuit comprising:

a phase locked loop unit for generating a clock signal based on a first reference data signal;

a delay locked loop unit for receiving the clock signal from the phase locked loop, dividing the clock signal into a plurality of clock signals and outputting the plurality of clock signals; and

a digital clock data recovery unit for receiving an input current signal, estimating a frequency of the input current signal, outputting a second reference data signal having the frequency to the phase locked loop unit, receiving the plurality of clock signals from the delay locked loop, aligning a phase of the input current signal based on the plurality of clock signals and outputting an aligned current signal.

2. The clock data recovery circuit of claim 1, wherein the second reference data signal is the first reference data signal.

3. The clock data recovery circuit of claim 1, wherein the phase locked loop unit comprises a charge pump, a voltage-controlled oscillator and a frequency divider.

4. The clock data recovery circuit of claim 3, wherein the phase locked loop unit further comprises a charge pump comparator.

5. The clock data recovery circuit of claim 4, wherein the phase locked loop unit further comprises a control logic.

6. The clock data recovery circuit of claim 1, wherein the delay locked loop unit comprises a phase detector, a loop filter and a voltage controlled delay line.

7. The clock data recovery circuit of claim 1, wherein the digital clock data recovery unit comprises a phase/frequency detector, a sampler, a phase alignment unit, an edge detector, a phase rotator, an up/down counter and a digital loop filter.

8. The clock data recovery circuit of claim 7, wherein the phase/frequency detector is configured to initiate from the lowest possible clock frequency.

9. The clock data recovery circuit of claim 1, further comprising a programmable equalizer for equalizing the input current signal before it is received by the digital current data recovery unit.

10. The clock data recovery circuit of claim 1, further comprising a first in first out buffer for receiving the aligned current signal from the digital current data recovery unit, a pseudorandom binary sequence generator or a pseudorandom binary sequence checker.

11. The clock data recovery circuit of claim 1, wherein the clock data recovery circuit is configured to correct a current signal having a frequency from about 2.5 gigahertz to about 30 gigahertz.

12. The clock data recovery circuit of claim 1, wherein the input current signal is clockless.

13. A clock data recovery circuit comprising:

a phase locked loop unit comprising a phase detector, a loop filter and a voltage controlled oscillator; and

a digital clock data recovery unit comprising a phase/frequency detector, a sampler, a phase alignment unit, an edge detector, a phase rotator, an up/down counter and a digital loop filter.

14. The clock data recovery circuit of claim 13, wherein the phase locked loop unit further comprises a control logic.

15. The clock data recovery circuit of claim 13, further comprising a programmable equalizer for equalizing the input current signal before it is received by the digital current data recovery unit.

16. The clock data recovery circuit of claim 13, further comprising a first in first out buffer for receiving the aligned current signal from the digital current data recovery unit, a pseudorandom binary sequence generator or a pseudorandom binary sequence checker.

17. The clock data recovery circuit of claim 13, wherein the clock data recovery circuit is configured to correct a current signal having a frequency from about 2.5 gigahertz to about 30 gigahertz.

18. The clock data recovery circuit of claim 13, wherein the input current signal is clockless.