METHOD FOR FABRICATING NANO DEVICES

• US 20120009749A1
• Filed: 07/08/2010
• Published: 01/12/2012
• Est. Priority Date: 07/08/2010
• Status: Active Grant

• Current Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.), Nanyang Technology University
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.), Nanyang Technology University
• Inventors: TAN, Dexter, PEY, Kin Leong, YEONG, Sai Hooi, NG, Chee Mang, CHIN, Yoke King, ONG, Kuang Kian
• Granted Patent: US 8,338,280 B2
• Time in Patent Office: Days
• US Class Current: 438/284
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/7613 Single electron transistors; Coulomb blockade devices H01L29/7888 takes precedence

Abstract

Embodiments relate to a method for fabricating nano-wires in nano-devices, and more particularly to nano-device fabrication using end-of-range (EOR) defects. In one embodiment, a substrate with a surface crystalline layer over the substrate is provided and EOR defects are created in the surface crystalline layer. One or more fins with EOR defects embedded within is formed and oxidized to form one or more fully oxidized nano-wires with nano-crystals within the core of the nano-wire.

Claims

1. A method for fabricating a semiconductor device comprising:

providing a substrate with a surface crystalline layer over the substrate;

creating end-of-range (EOR) defects in the surface crystalline layer;

forming one or more fins with EOR defects embedded within; and

oxidizing the one or more fins to form one or more fully oxidized nano-wires with nano-crystals within the core of the nano-wires.

2. The method of claim 1 wherein creating EOR defects comprises:

performing a pre-amorphization implant (PAI) on the surface crystalline layer to form an amorphous silicon layer above the surface crystalline layer; and

annealing the substrate to recrystallize the amorphous silicon layer as well as form EOR defects.

3. The method of claim 2, wherein the PAI implants Si+ or Ge+ ions at a dose from 1×

10¹⁵ cm<sup>−

2</sup> to 1×

10¹⁷ cm<sup>−

2</sup> into the surface crystalline layer and may be performed at different energy levels to form EOR defects at different depths from the top of the surface crystalline layer.

4. The method of claim 2, wherein the PAI and annealing steps may be repeatedly performed one after the other at different depths from the top of the surface crystalline layer for 2 or more times to form multiple levels of EOR defects thereby resulting in twin or multiple defect layered nano-wires.

5. The method of claim 2, wherein the PAI and annealing steps may be performed one after the other at different depths from the top of the surface crystalline layer for 2 times to form a twin column of nano-wires.

6. The method of claim 1 wherein the one or more fins is formed before the EOR defects are created.

7. The method of claim 1 wherein forming the one of more fins comprises:

depositing a hard mask layer to selectively expose portions of the substrate to be removed;

etching the exposed portions to form one or more fins; and

removing the hard mask layer, wherein the usage of the hard mask allows for a more conformal sidewall etching.

8. The method of claim 2 wherein a soft mask with an anti-reflective coating beneath it is formed and patterned on the substrate surface before EOR defects are created in the surface crystalline layer.

9. The method of claim 8 wherein the soft mask is removed before the substrate is annealed to recrystallize the amorphous silicon layer as well as form EOR defects, wherein the anneal is a low temperature anneal and serves to stabilize the EOR defects by increasing the defects'"'"' resistance and dissolution stability.

10. The method of claim 1 wherein oxidation is achieved by subjecting the one or more fins to an anneal in an oxidizing ambient at the temperature of 1100°

C. for 5 hours.

11. A method for fabricating a semiconductor device comprising:

providing a substrate with a surface crystalline layer over the substrate;

creating end-of-range (EOR) defects in the surface crystalline layer;

forming one or more fins with EOR defects embedded within;

oxidizing the one or more fins;

removing the oxide from the one or more fins to form one or more nano-wires; and

oxidizing the one or more nano-wires to form one or more fully oxidized nano-wires with nano-crystals within the core of the nano-wires.

12. The method of claim 11 wherein the oxide is removed from the one or more fins and a pad region using a wet etch.

13. The method of claim 12 wherein the surface crystalline layer is patterned using a hard mask layer to form in the pad region a first and second contact pads coupled by the nano-wire.

14. The method of claim 13 wherein a gate layer is further deposited on the substrate and patterned to form a gate that is separated from the first and second contact pads and covers the nano-wire, wherein the gate layer is about 1300 Å

.

15. The method of claim 14 wherein the contact pads are doped when the gate is being formed after the gate is patterned, wherein the nano-wire covered by the gate serves as a channel of a SET.

16. The method of claim 11 wherein creating EOR defects comprises:

performing a pre-amorphization implant (PAI) on the surface crystalline layer to form an amorphous silicon layer above the surface crystalline layer; and

annealing the substrate to recrystallize the amorphous silicon layer as well as form EOR defects, wherein the PAI implants Si+ or Ge+ ions at a high dose from 1×

10¹⁵ cm<sup>−

2</sup> to 1×

10¹⁷ cm<sup>−

2</sup> into the surface crystalline layer and may be performed at different energy levels to form EOR defects at different depths from the top of the surface crystalline layer.

17. The method of claim 16, wherein the PAI and annealing steps may be performed one after the other at different depths from the top of the surface crystalline layer for 2 or more times to form multiple levels of EOR defects thereby resulting in twin or multiple defect layered nano-wires.

18. The method of claim 16 wherein the PAI does not fully amorphize the entire surface crystalline layer.

19. The method of claim 16 wherein the substrate may be patterned to form one or more fins using a hard mask prior to performing a PAI using a soft mask to form EOR defects.

20. The method of claim 11 wherein oxidation is achieved by subjecting the one or more fins to an anneal in an oxidizing ambient at the temperature of 1100°

C. for 5 hours.

21. A method for fabricating a semiconductor device comprising:

providing a substrate with a surface crystalline layer over the substrate;

performing a pre-amorphization implant (PAI) on the surface crystalline layer to form an amorphous silicon layer above the surface crystalline layer;

annealing the substrate to recrystallize the amorphous silicon layer as well as form EOR defects;

depositing a hard mask layer to selectively expose portions of the substrate to be removed;

etching the exposed portions to form one or more fins;

removing the hard mask layer, wherein the usage of the hard mask allows for a more conformal sidewall etching; and

oxidizing the one or more fins to form one or more fully oxidized nano-wires with nano-crystals within the core of the nano-wires.