Memory device with dynamic controllable physical logical mapping table loading

• US 20120011299A1
• Filed: 07/09/2010
• Published: 01/12/2012
• Est. Priority Date: 07/09/2010
• Status: Active Grant

• Current Assignee: Memory Technologies LLC (Pendrell Corporation)
• Original Assignee: Nokia Corporation
• Inventors: Mylly, Kimmo J.
• Granted Patent: US 8,285,920 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages

Abstract

An apparatus includes a processor and a memory that includes computer program code. The memory and the computer program code are configured to, with the processor, cause the apparatus at least to send information from a host device to a mass storage memory device that is connected with the host device, the information including an indication of at least one default logical address range for a mass memory of the mass storage memory device. The memory and the computer program code are further configured, with the processor, to cause the apparatus, during operation of the host device with the mass storage memory device, and in response to at least one trigger condition being satisfied, to initiate a load of a portion of a logical-physical address conversion table that is stored in a memory of the mass storage memory device to another memory of the mass storage memory device as a local logical-physical address conversion table, where the portion corresponds to the at least one default logical address range. Also disclosed are corresponding methods and computer-readable storage medium, as well as a mass memory device or module that operates and is constructed in accordance with the exemplary embodiments of this invention.

Claims

1. A method, comprising:

sending information from a host device to a mass storage memory device that is connected with the host device, the information comprising an indication of at least one default logical address range for a mass memory of the mass storage memory device; and

during operation of the host device with the mass storage memory device, and in response to at least one trigger condition being satisfied, initiating a load of a portion of a logical-physical address conversion table that is stored in a memory of the mass storage memory device to another memory of the mass storage memory device as a local logical-physical address conversion table, where the portion corresponds to the at least one default logical address range.

2. The method of claim 1, where the at least one default logical address range is a pre-determined logical address range, and where the indication specifies one of the at least one default logical address range or a starting address of the at least one default logical address range.

3. The method of claim 2, where the at least one pre-determined default logical address range is modified based on at least one of a change in a software program and an installation of a new software program in the host device.

4. The method as in claim 2, where the at least one pre-determined default logical address range is modified by a controller of the mass storage memory device during operation of the mass memory storage device.

5. The method as in claim 1, further comprising receiving from the mass memory storage device at least one parameter that specifies at least a size of a portion of the another memory that is allocated to store the portion of the logical-physical address conversion table as the local logical-physical address conversion table, and where the information that is sent from the host device to the mass storage memory device is determined by the host device at least in part based on the at least one parameter that is received from the mass storage memory device.

6. The method of claim 5, where the at least one parameter further specifies how many local logical-physical address conversion tables are stored in the mass memory storage device.

7. The method of claim 6, where the at least one parameter further specifies a size of each of the local logical-physical address conversion tables that are stored in the mass memory storage device.

8. The method as in claim 1, where the at least one trigger condition is comprised of at least one of power up, reset, a defined delay and a transition from a low power mode of operation to a higher power mode of operation.

9. A non-transitory computer-readable medium that contains software program instructions, where execution of the software program instructions by at least one data processor results in performance of operations that comprise execution of the method of claim 1.

10. An apparatus, comprising:

a processor; and

a memory including computer program code, where the memory and computer program code are configured to, with the processor, cause the apparatus at least to,

send information from a host device to a mass storage memory device that is connected with the host device, the information comprising at least one default logical address range for a mass memory of the mass storage memory device; and

during operation of the host device with the mass storage memory device, and in response to at least one trigger condition being satisfied, initiate a load of a portion of a logical-physical address conversion table that is stored in a memory of the mass storage memory device to another memory of the mass storage memory device as a local logical-physical address conversion table, where the portion corresponds to the at least one default logical address range.

11. The apparatus of claim 10, where the at least one default logical address range is a pre-determined logical address range, and where the indication specifies one of the at least one default logical address range or a starting address of the at least one default logical address range.

12. The apparatus of claim 11, where the at least one pre-determined default logical address range is modified based on at least one of a change in a software program and the installation of a new software program in the host device.

13. The apparatus as in claim 11, where the at least one pre-determined default logical address range is modified by a controller of the mass storage memory device during operation of the mass memory storage device.

14. The apparatus as in claim 10, further comprising controlling the processor to receive from the mass memory storage device at least one parameter that specifies at least a size of a portion of the random access memory that is allocated to store the portion of the logical-physical address conversion table as the local logical-physical address conversion table, and where the information that is sent from the host device to the mass storage memory device is determined by the host device at least in part based on the at least one parameter that is received from the mass storage memory device.

15. The apparatus of claim 14, where the at least one parameter further specifies how many local logical-physical address conversion tables are stored in the mass memory storage device.

16. The apparatus of claim 15, where the at least one parameter further specifies a size of each of the local logical-physical address conversion tables that are stored in the mass memory storage device.

17. The apparatus as in claim 10, where the at least one trigger condition is comprised of at least one of power up, reset, a defined delay and a transition from a low power mode of operation to a higher power mode of operation.

18. A method, comprising:

during operation of a mass storage memory device, detecting at least one trigger condition being satisfied; and

in response, initiating a load of a portion of a logical-physical address conversion table that is stored in a memory of the mass storage memory device to another memory of the mass storage memory device as a local logical-physical address conversion table, where the portion corresponds to at least one default logical address range.

19. The method as in claim 18, further comprising receiving information at the mass memory storage device from a host device that is connected with the mass memory storage device, the information comprising an indication of the at least one pre-determined default logical address range for a mass memory of the mass storage memory device.

20. The method as in claim 18, where the at least one pre-determined default logical address range is modifiable during operation of the mass memory storage device so as to enable the loading of a different portion of the logical-physical address conversion table to the another memory of the mass storage memory device as the local logical-physical address conversion table.

21. The method as in claim 18, further comprising sending from the mass memory storage device at least one parameter that specifies at least a size of a portion of the another memory that is allocated to store the portion of the logical-physical address conversion table as the local logical-physical address conversion table.

22. The method of claim 21, where the at least one parameter further specifies how many local logical-physical address conversion tables are stored in the mass memory storage device and a size of each of the local logical-physical address conversion tables that are stored in the mass memory storage device.

23. The method as in claim 18, where the at least one trigger condition is comprised of at least one of power up, reset, a defined delay and a transition from a low power mode of operation to a higher power mode of operation.

24. The method as in claim 19, where the mass storage memory device is configured to change the default loading and contents of the portion of the logical-physical address conversion table based on at least one of information received from the host device, a command received from the host device, and mass memory access statistics recorded by a controller of the mass storage memory device.

25. An apparatus, comprising:

a processor; and

a memory including computer program code, where the memory and computer program code are configured, with the processor, cause the apparatus at least to,

during operation of the mass storage memory device, and in response to at least one trigger condition being satisfied, initiate a load of a portion of a logical-physical address conversion table that is stored in a memory of the mass storage memory device to another memory of the mass storage memory device as a local logical-physical address conversion table, where the portion corresponds to at least one default logical address range.

26. The apparatus as in claim 25, where said data processor is further configured to receive information at the mass memory storage device from a host device that is connected with the mass memory storage device, the information comprising the at least one pre-determined default logical address range for the mass memory of the mass storage memory device.

27. The apparatus as in claim 25, where the at least one pre-determined default logical address range is modifiable by said data processor during operation of the mass memory storage device so as to enable the loading of a different portion of the logical-physical address conversion table to the another memory of the mass storage memory device as the local logical-physical address conversion table.

28. The apparatus as in claim 26, further comprising a memory element configured to store at least one parameter that specifies at least a size of a portion of the another memory that is allocated to store the portion of the logical-physical address conversion table as the local logical-physical address conversion table, and where said data processor is configured to send the at least one parameter to the host device.

29. The apparatus as in claim 28, where the at least one parameter further specifies how many local logical-physical address conversion tables are stored in the mass memory storage device and a size of each of the local logical-physical address conversion tables that are stored in the mass memory storage device.

30. The apparatus as in claim 25, where the at least one trigger condition is comprised of at least one of power up, reset, a defined delay and a transition from a low power mode of operation to a higher power mode of operation.

31. The apparatus as in claim 25, where said data processor is configured to change the default loading and contents of the portion of the logical-physical address conversion table based on at least one of information received from the host device, a command received from the host device, and mass memory access statistics recorded by said data processor.