ARCHITECTURES FOR IMAGER ARRAYS AND ARRAY CAMERAS

• US 20120012748A1
• Filed: 05/12/2011
• Published: 01/19/2012
• Est. Priority Date: 05/12/2010
• Status: Abandoned Application

• Current Assignee: Fotonation Cayman Limited
• Original Assignee: Pelican Imaging Corporation
• Inventors: McMahon, Andrew Kenneth John, Pain, Bedabrato
• Application Number:
  US13/106,797
• Publication Number:
  US 20120012748A1
• Time in Patent Office: Days
• US Class Current: 250/332
• CPC Class Codes: H04N 23/13 with multiple sensors
• CPC Class Codes: H04N 23/951 by using two or more images to influence resolution, frame rate or aspect ratio
• CPC Class Codes: H04N 25/134 based on three different wavelength filter elements
• CPC Class Codes: H04N 25/40 Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
• CPC Class Codes: H04N 25/41 Extracting pixel data from a plurality of image sensors simultaneously picking up an image, e.g. for increasing the field of view by combining the outputs of a plurality of sensors
• CPC Class Codes: H04N 25/44 by partially reading an SSIS array
• CPC Class Codes: H04N 25/672 between adjacent sensors or output registers for reading a single image
• CPC Class Codes: H04N 25/704 Pixels specially adapted for focusing, e.g. phase difference pixel sets
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/767 Horizontal readout lines, multiplexers or registers
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/772 comprising A/D, V/T, V/F, I/T or I/F converters
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

Architectures for imager arrays configured for use in array cameras in accordance with embodiments of the invention are described. One embodiment of the invention includes a plurality of focal planes, where each focal plane comprises a two dimensional arrangement of pixels having at least two pixels in each dimension and each focal plane is contained within a region of the imager array that does not contain pixels from another focal plane, control circuitry configured to control the capture of image information by the pixels within the focal planes, where the control circuitry is configured so that the capture of image information by the pixels in at least two of the focal planes is separately controllable, and sampling circuitry configured to convert pixel outputs into digital pixel data.

Claims

21-1. The imager array of claim 1, wherein at least one of the focal planes includes an array of adjacent pixels, where the pixels in the array of adjacent pixels are configured to capture different colors of light.

52. The imager array of 51, wherein:

the control circuitry is configured to separately control the power down state of the focal plane'"'"'s associated AFE circuitry or processing timeslot therein; and

the control circuitry is configured to power down the focal plane'"'"'s associated AFE circuitry or processing timeslot therein without powering down the associated AFE circuitry or processing timeslot therein for readout of the reference pixels of the focal plane.