Metal Oxide Semiconductor Thin Film Transistors

• US 20120012835A1
• Filed: 07/14/2010
• Published: 01/19/2012
• Est. Priority Date: 07/14/2010
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Herman, Gregory, Maa, Jer-shen, Voutsas, Apostolos T., Puntambekar, Kanan
• Granted Patent: US 8,513,720 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02581 Transition metal or rare earth elements
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A top gate and bottom gate thin film transistor (TFT) are provided with an associated fabrication method. The TFT is fabricated from a substrate, and an active metal oxide semiconductor (MOS) layer overlying the substrate. Source/drain (S/D) regions are formed in contact with the active MOS layer. A channel region is interposed between the S/D regions. The TFT includes a gate electrode, and a gate dielectric interposed between the channel region and the gate electrode. The active MOS layer may be ZnOx, InOx, GaOx, SnOx, or combinations of the above-mentioned materials. The active MOS layer also includes a primary dopant such as H, K, Sc, La, Mo, Bi, Ce, Pr, Nd, Sm, Dy, or combinations of the above-mentioned dopants. The active MOS layer may also include a secondary dopant.

Claims

1. A top gate thin film transistor (TFT) comprising:

a substrate;

an active metal oxide semiconductor (MOS) layer overlying the substrate;

source/drain (S/D) regions in contact with the active MOS layer;

a channel region interposed between the S/D regions;

a gate electrode;

a gate dielectric interposed between the channel region and the gate electrode; and

,

wherein the active MOS layer is selected from a group consisting of ZnOx, InOx, GaOx, SnOx, and combinations of the above-mentioned materials, and includes a primary dopant selected from a group consisting of H, K, Sc, La, Mo, Bi, Ce, Pr, Nd, Sm, Dy, and combinations of the above-mentioned dopants.

2. The top gate TFT of claim 1 wherein the active MOS layer is selected from a group consisting of ZnSnOx, InGaZnOx, ZnInOx, and InGaOx.

3. The top gate TFT of claim 2 wherein the primary dopant is selected from a group consisting of H, Mo, and a combination of H and Mo.

4. The top gate TFT in claim 2 wherein the active MOS layer is InGaZnOx and the primary dopant is Mo.

5. The top gate TFT of claim 1 wherein the active MOS layer includes a secondary dopant selected from a group consisting of Li, Na, Mg, Ca, Sr, Y, Ti, Zr, V, Nb, Ta, W, Mn, Ru, Ni, Pd, Cu, Ag, Cd, Pb, Ge, Si, C, B, Al, N, P, Sb, F, and combinations of the above-mentioned dopants.

6. A bottom gate thin film transistor (TFT) comprising:

a substrate;

a gate electrode overlying the substrate;

a gate dielectric overlying the gate electrode;

an active metal oxide semiconductor (MOS) layer overlying the gate dielectric;

source/drain (S/D) regions in contact with the active MOS layer;

a channel region formed in the active MOS layer, interposed between the S/D regions; and

,

wherein the active MOS layer is selected from a group consisting of ZnOx, InOx, GaOx, SnOx, and combinations of the above-mentioned materials, with a primary dopant selected from a group consisting of H, K, Sc, La, Mo, Bi, Ce, Pr, Nd, Sm, Dy, and combinations of the above-mentioned dopants.

7. The bottom gate TFT of claim 6 wherein the active MOS layer is selected from a group consisting of ZnSnOx, InGaZnOx, ZnInOx, and InGaOx.

8. The bottom gate TFT of claim 7 wherein the primary dopant is selected from a group consisting of H, Mo, and a combination of H and Mo.

9. The bottom gate TFT in claim 7 wherein the active MOS layer is InGaZnOx and the primary dopant is Mo.

10. The bottom gate TFT of claim 6 wherein the active MOS layer includes a secondary dopant selected from a group consisting of Li, Na, Mg, Ca, Sr, Y, Ti, Zr, V, Nb, Ta, W, Mn, Ru, Ni, Pd, Cu, Ag, Cd, Pb, Ge, Si, C, B, Al, N, P, Sb, F, and combinations of the above-mentioned dopants.

11. A method for forming a thin film transistor (TFT) comprising:

forming a substrate;

forming an active metal oxide semiconductor (MOS) layer overlying the substrate, selected from a group of materials consisting of ZnOx, InOx, GaOx, SnOx, and combinations of the above-mentioned materials, and including a primary dopant selected from a group consisting of H, K, Sc, La, Mo, Bi, Ce, Pr, Nd, Sm, Dy, and combinations of the above-mentioned dopants;

forming source/drain (S/D) regions in contact with the active MOS layer;

forming a channel region interposed between the S/D regions;

forming a gate electrode selected from a group consisting of a top gate electrode and a bottom gate electrode; and

,

forming a gate dielectric interposed between the channel region and the gate electrode.

12. The method of claim 11 wherein forming the active MOS layer includes using a vacuum-based deposition technique selected from a group consisting of dc sputtering, RF sputtering, magnetron sputtering, and ion beam sputtering.

13. The method of claim 11 wherein forming the active MOS layer includes using a solution-based deposition technique, selected from a group consisting of blanket spin-coating and patterned printing techniques, followed by an anneal process.

14. The method of claim 11 wherein forming the active MOS layer includes forming the active MOS layer with a secondary dopant selected from a group consisting of Li, Na, Mg, Ca, Sr, Y, Ti, Zr, V, Nb, Ta, W, Mn, Ru, Ni, Pd, Cu, Ag, Cd, Pb, Ge, Si, C, B, Al, N, P, Sb, F, and combinations of the above-mentioned dopants.

15. The method of claim 14 wherein forming the active MOS layer includes introducing a combination of the primary dopant and the secondary dopant using a method selected from a group consisting of sputtering with a target modified to include the dopants and implantation.

16. The method of claim 14 wherein forming the active MOS layer includes introducing a combination of the primary dopant and the secondary dopant by the deposition of an additional film including the dopants, on a surface selected from a group consisting of a top and a bottom active MOS layer surface, followed by an annealing step to diffuse the dopant through the bulk of the active MOS layer.

17. The method of claim 11 wherein forming the active MOS layer includes introducing the primary dopant using a method selected from a group consisting of sputtering with a target modified to include the dopants and implantation.

18. The method of claim 11 wherein forming the active MOS layer includes introducing the primary dopant by the deposition of an additional film including the dopant, on a surface selected from a group consisting of a top and a bottom active MOS layer surface, followed by an annealing step to diffuse the dopant through the bulk of the active MOS layer.

19. The method of claim 11 wherein forming the active MOS layer includes:

introducing a primary dopant as an element of a gas to the previously deposited active MOS layer at a first partial pressure to create a first electron carrier concentration at an interface of the active MOS layer and gate dielectric layer; and

,

introducing the primary dopant at a second partial pressure, less than the first partial pressure, to create a second electron carrier concentration, less than the first electron carrier concentration, in the active MOS layer away from the interface.