WIDE-GAP SEMICONDUCTOR SUBSTRATE AND METHOD TO FABRICATE WIDE-GAP SEMICONDUCTOR DEVICE USING THE SAME

• US 20120012857A1
• Filed: 01/04/2011
• Published: 01/19/2012
• Est. Priority Date: 07/13/2010
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: KURAGUCHI, Masahiko
• Granted Patent: US 8,841,681 B2
• Time in Patent Office: Days
• US Class Current: 257/76
• CPC Class Codes: G03F 9/7076 Mark details, e.g. phase grating mark, temporary mark
• CPC Class Codes: G03F 9/708 Mark formation
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A wide-gap semiconductor substrate includes a narrow-gap semiconductor layer, a wide-gap semiconductor layer and an alignment mark. The narrow-gap semiconductor layer has a main surface. The wide-gap semiconductor layer is epitaxially grown on the narrow-gap semiconductor layer. The alignment mark is preliminarily carved in a prescribed position on the main surface so that the alignment mark is preliminarily buried in the wide-gap semiconductor substrate.

Claims

1. A wide-gap semiconductor substrate comprising:

a narrow-gap semiconductor layer having a main surface;

a wide-gap semiconductor layer which is epitaxially grown on the narrow-gap semiconductor substrate; and

an alignment mark which is preliminarily carved in a prescribed position on the main surface so that the alignment mark is buried in the wide-gap semiconductor substrate.

2. The substrate according to claim 1, wherein the narrow-gap semiconductor layer is a Si layer and the wide-gap semiconductor layer includes a nitride semiconductor.

3. The substrate according to claim 2, wherein a plane direction of the Si layer is (111) and a thickness of the wide-gap semiconductor layer is 2d or more on an area of the Si layer where the alignment mark is not formed when d represents a depth of carved concaves of the alignment mark.

4. The substrate according to claim 2, wherein a plane direction of the Si layer is (111) and a distance is 2d, the distance being from a bottom of carved concaves of the alignment mark to a surface of the wide-gap semiconductor layer, when d represents a depth of carved concaves of the alignment mark.

5. A method to fabricate a wide gap semiconductor device on a wide-gap semiconductor substrate, comprising:

applying resist to the wide-gap semiconductor substrate, the wide-gap semiconductor substrate including;

a narrow-gap semiconductor layer having a main surface;

a wide-gap semiconductor layer which is epitaxially grown on the narrow-gap semiconductor substrate; and

an alignment mark which is preliminarily carved in a prescribed position on the main surface so that the alignment mark is buried in the wide-gap semiconductor substrate, and

irradiating the alignment mark with visible light and detecting light reflected from the alignment mark to align the wide-gap semiconductor substrate.

6. The method according to claim 5, wherein

the wide-gap semiconductor device includes a field-effect transistor;

and

the alignment mark is irradiated with visible light and light reflected therefrom is detected to determine positions of a drain, a source and a gate of the field-effect transistor.