Substrate Stand-Offs for Semiconductor Devices

• US 20120012985A1
• Filed: 07/13/2010
• Published: 01/19/2012
• Est. Priority Date: 07/13/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Kuo, Tin-Hao, Kuo, Chen-Cheng, Chen, Chen-Shien, Chuang, Yao-Chun, Shen, Cheng Hung
• Granted Patent: US 8,227,924 B2
• Time in Patent Office: Days
• US Class Current: 257/618
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05073 Single internal layer
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05681 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/11444 in gaseous form
• CPC Class Codes: H01L 2224/1145 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/11452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13012 in top view
• CPC Class Codes: H01L 2224/13014 being circular or elliptic
• CPC Class Codes: H01L 2224/13015 comprising protrusions or indentations
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13124 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13169 : Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/1403 : Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14051 : Bump connectors having different shapes
• CPC Class Codes: H01L 2224/14131 : being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/14179 : Corner adaptations, i.e. disposition of the bump connectors at the corners of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/14515 : Bump connectors having different functions
• CPC Class Codes: H01L 2224/14517 : including bump connectors providing primarily mechanical bonding
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/17051 : Bump connectors having different shapes
• CPC Class Codes: H01L 2224/17517 : including bump connectors providing primarily mechanical support
• CPC Class Codes: H01L 2224/29011 : comprising apertures or cavities
• CPC Class Codes: H01L 2224/29013 : being rectangular or square
• CPC Class Codes: H01L 2224/29101 : the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/29111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/83193 : wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 23/3171 : the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/3192 : Multilayer coating
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/1579 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

Substrate stand-offs for use with semiconductor devices are provided. Active pillars and dummy pillars are formed on a first substrate such that the dummy pillars may have a height greater than a height of the active pillars. The dummy pillars act as stand-offs when joining the first substrate to a second substrate, thereby creating greater uniformity. In an embodiment, the dummy pillars may be formed simultaneously as the active pillars by forming a patterned mask having openings with a smaller width for the dummy pillars than for the active pillars. When an electro-plating process of the like is used to form the dummy and active pillars, the smaller width of the dummy pillar openings in the patterned mask causes the dummy pillars to have a greater height than the active pillars.

Claims

1. A semiconductor structure comprising:

a first substrate;

an active pillar on the first substrate, the active pillar having a first width and a first height; and

a dummy pillar on the first substrate, the dummy pillar having a second width and a second height, the second width being less than the first width, the second height being greater than the first height.

2. The semiconductor structure of claim 1, wherein a ratio of the second width to the first width is equal to or greater than about 0.2 and equal to less than about 0.9.

3. The semiconductor structure of claim 1, wherein a cross section of the dummy pillar along a plane parallel to the first substrate is circular.

4. The semiconductor structure of claim 1, wherein a cross section of the dummy pillar along a plane parallel to the first substrate has a plurality of linear edges.

5. The semiconductor structure of claim 1, wherein a cross section of the dummy pillar along a plane parallel to the first substrate comprises a first portion having a first longitudinal axis and a second portion having a second longitudinal axis, the first longitudinal axis intersecting the second longitudinal axis.

6. The semiconductor structure of claim 1, further comprising a second substrate attached to the first substrate, the second substrate having a solder resist mask, the dummy pillar extending into an opening in the solder resist.

7. The semiconductor structure of claim 1, further comprising a second substrate attached to the first substrate, the second substrate having a solder resist mask, the dummy pillar contacting an upper surface of the solder resist.

8. A semiconductor structure comprising:

a first substrate;

a plurality of active pillars on the first substrate, the plurality of active pillars being electrically active; and

a plurality of dummy pillars on the first substrate, each dummy pillar being electrically inactive, the dummy pillars having a first width less than a second width of the active pillars.

9. The semiconductor structure of claim 8, wherein a ratio of the first width to the second width is equal to or greater than about 0.2 and equal to less than about 0.9.

10. The semiconductor structure of claim 8, further comprising a second substrate attached to the first substrate such that the plurality of dummy pillars extends through openings in an upper layer of the second substrate.

11. The semiconductor structure of claim 8, further comprising a second substrate attached to the first substrate such that the plurality of dummy pillars contacts an uppermost surface of the second substrate.

12. The semiconductor structure of claim 8, wherein the plurality of dummy pillars includes dummy pillars in one or more corners of the first substrate.

13. The semiconductor structure of claim 8, wherein the plurality of dummy pillars includes one or more dummy pillars along an edge between adjacent corners of the first substrate.

14. The semiconductor structure of claim 8, wherein the plurality of dummy pillars includes one or more pillars in an interior portion of the first substrate.

15. A method of forming a device, the method comprising:

providing a first substrate having one or more electrical contacts;

forming a patterned mask over the substrate, the patterned mask having dummy pillar openings and active pillar openings;

forming dummy pillars in the dummy pillar openings and forming active pillars in the active pillar openings, a width of the dummy pillars being less than a width of the active pillars; and

removing the patterned mask.

16. The method of claim 15, wherein at least some of the dummy pillars are positioned in corners of the substrate.

17. The method of claim 16, wherein at least some of the dummy pillars are positioned along an edge of the substrate between adjacent corners.

18. The method of claim 15, further comprising attaching the first substrate to a second substrate.

19. The method of claim 18, wherein the second substrate has a solder resist formed thereon and the dummy pillars contact an upper surface of the solder resist.

20. The method of claim 18, wherein the second substrate has a solder resist formed thereon and the dummy pillars extend into respective openings in the solder resist.