Semiconductor Device and Method of Forming Protective Layer Over Exposed Surfaces of Semiconductor Die

• US 20120012990A1
• Filed: 07/16/2010
• Published: 01/19/2012
• Est. Priority Date: 07/16/2010
• Status: Active Grant

• Current Assignee: Stats Chippac Limited
• Original Assignee: Stats Chippac Limited
• Inventors: Pagaila, Reza A., Choi, DaeSik, Koo, Jun Mo
• Granted Patent: US 8,642,381 B2
• Time in Patent Office: Days
• US Class Current: 257/659
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/06102 the bonding areas being at different heights
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/1132 Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/1145 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/11464 Electroless plating
• CPC Class Codes: H01L 2224/11849 Reflowing
• CPC Class Codes: H01L 2224/11901 with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13113 Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/13116 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13124 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/2101 : Structure
• CPC Class Codes: H01L 2224/214 : Connecting portions
• CPC Class Codes: H01L 2224/221 : Disposition
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48145 : the bodies being stacked
• CPC Class Codes: H01L 2224/73207 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73209 : Bump and HDI connectors
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/83192 : wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/9211 : Parallel connecting processes
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3185 : the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 23/34 : Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. A shielding layer is formed between the first and second semiconductor die. An electrical interconnect, such as conductive pillar, bump, or bond wire, is formed between the first and second semiconductor die. A conductive TSV can be formed through the first and second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and electrical interconnect. A heat sink is formed over the second semiconductor die. An interconnect structure, such as a bump, can be formed over the second semiconductor die. A portion of a backside of the first semiconductor die is removed. A protective layer is formed over exposed surfaces of the first semiconductor die. The protective layer covers the exposed backside and sidewalls of the first semiconductor die.

Claims

1. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor wafer having a plurality of first semiconductor die;

forming a plurality of conductive pillars over the semiconductor wafer;

mounting a second semiconductor die between the conductive pillars to the first semiconductor die;

depositing an encapsulant over the first and second semiconductor die and conductive pillars;

removing a portion of a backside of the second semiconductor die and encapsulant to expose the conductive pillars;

forming an interconnect structure over the backside of the second semiconductor die, encapsulant, and conductive pillars;

leading with the interconnect structure, mounting the semiconductor wafer to a temporary carrier;

removing a portion of a backside of the semiconductor wafer;

singulating the semiconductor wafer without cutting through the encapsulant and carrier;

forming a protective layer over exposed surfaces of the first semiconductor die;

removing the temporary carrier; and

singulating the semiconductor wafer into individual semiconductor devices.

2. The method of claim 1, wherein the protective layer covers the exposed backside and sidewalls of the first semiconductor die.

3. The method of claim 1, further including forming a conductive via through the first semiconductor die.

4. The method of claim 1, further including forming a conductive via through the second semiconductor die.

5. The method of claim 1, further including applying penetrable tape to the temporary carrier for mounting the interconnect structure.

6. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor wafer having a plurality of first semiconductor die;

mounting a second semiconductor die to the first semiconductor die;

forming an electrical interconnect between the first and second semiconductor die;

depositing an encapsulant over the first and second semiconductor die and electrical interconnect; and

forming a protective layer over exposed surfaces of the first semiconductor die.

7. The method of claim 6, wherein the protective layer covers the exposed backside and sidewalls of the first semiconductor die.

8. The method of claim 6, wherein the electrical interconnect includes a conductive pillar, bond wire, or bump.

9. The method of claim 6, further including forming an interconnect structure over the second semiconductor die.

10. The method of claim 9, wherein the interconnect structure includes a bump.

11. The method of claim 6, further including removing a portion of a backside of the first semiconductor die prior to forming the protective layer.

12. The method of claim 6, further including forming a shielding layer between the first and second semiconductor die.

13. The method of claim 6, further including forming a heat sink over the second semiconductor die.

14. A method of manufacturing a semiconductor device, comprising:

providing a first semiconductor die;

mounting a second semiconductor die to the first semiconductor die;

forming an electrical interconnect between the first and second semiconductor die;

depositing an encapsulant over the first and second semiconductor die; and

forming a protective layer over exposed surfaces of the first semiconductor die.

15. The method of claim 14, wherein the protective layer covers the exposed backside and sidewalls of the first semiconductor die.

16. The method of claim 14, wherein the electrical interconnect includes a conductive pillar, bond wire, or bump.

17. The method of claim 14, further including forming a shielding layer between the first and second semiconductor die.

18. The method of claim 14, further including forming a heat sink over the second semiconductor die.

19. The method of claim 14, further including forming an interconnect structure over the second semiconductor die.

20. A semiconductor device, comprising:

a first semiconductor die;

a second semiconductor die mounted to the first semiconductor die;

an electrical interconnect formed between the first and second semiconductor die;

an encapsulant deposited over the first and second semiconductor die and electrical interconnect; and

a protective layer formed over exposed surfaces of the first semiconductor die.

21. The semiconductor device of claim 20, wherein the protective layer covers the exposed backside and sidewalls of the first semiconductor die.

22. The semiconductor device of claim 20, wherein the electrical interconnect includes a conductive pillar, bond wire, or bump.

23. The semiconductor device of claim 20, further including an interconnect structure formed over the second semiconductor die.

24. The semiconductor device of claim 20, further including a shielding layer formed between the first and second semiconductor die.

25. The semiconductor device of claim 20, further including a heat sink formed over the second semiconductor die.