TEMPORARY SEMICONDUCTOR STRUCTURE BONDING METHODS AND RELATED BONDED SEMICONDUCTOR STRUCTURES

• US 20120013013A1
• Filed: 07/19/2010
• Published: 01/19/2012
• Est. Priority Date: 07/19/2010
• Status: Active Grant

• Current Assignee: Soitec S.A.
• Original Assignee: Soitec S.A.
• Inventors: Sadaka, Mariam, Radu, Ionut
• Granted Patent: US 8,461,017 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/03616 Chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 2224/0362 Photolithography
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05687 Ceramics, e.g. crystalline carbides, nitrides or oxides glass ceramics H01L2224/05688
• CPC Class Codes: H01L 2224/08121 the connected bonding areas being not aligned with respect to each other
• CPC Class Codes: H01L 2224/08146 the bonding area connecting to a via connection in the body
• CPC Class Codes: H01L 2224/0903 Bonding areas having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/27444 : in gaseous form
• CPC Class Codes: H01L 2224/27616 : Chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 2224/29187 : Ceramics, e.g. crystalline carbides, nitrides or oxides glass ceramics H01L2224/29188
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 2224/80006 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/80011 : Chemical cleaning, e.g. etching, flux
• CPC Class Codes: H01L 2224/80121 : Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
• CPC Class Codes: H01L 2224/802 : Applying energy for connecting
• CPC Class Codes: H01L 2224/80203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/80357 : being flush with the surface
• CPC Class Codes: H01L 2224/80805 : involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2224/80894 : Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/80895 : between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/80896 : between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/80905 : Combinations of bonding methods provided for in at least two different groups from H01L2224/808 - H01L2224/80904
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/83005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/83011 : Chemical cleaning, e.g. etching, flux
• CPC Class Codes: H01L 2224/83022 : Cleaning the bonding area, e.g. oxide removal step, desmearing
• CPC Class Codes: H01L 2224/83121 : Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
• CPC Class Codes: H01L 2224/83191 : wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83193 : wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/832 : Applying energy for connecting
• CPC Class Codes: H01L 2224/83203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/83205 : Ultrasonic bonding
• CPC Class Codes: H01L 2224/83805 : involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2224/83896 : between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2224/9211 : Parallel connecting processes
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/28 : Structure, shape, material or disposition of the layer connectors prior to the connecting process
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/98 : Methods for disconnecting semiconductor or solid-state bodies
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/05442 : SiO2
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.

Claims

1. A method of fabricating a semiconductor structure, comprising:

forming a first semiconductor structure including at least a portion of an integrated circuit on a first substrate;

implanting ions into a carrier wafer to form a weakened region within the carrier wafer;

directly bonding the carrier wafer to a first side of the first semiconductor structure;

processing the first semiconductor structure while the carrier wafer is attached to the first semiconductor structure using the carrier wafer to handle the first semiconductor structure;

directly bonding a second semiconductor structure including at least a portion of an integrated circuit to a second side of the first semiconductor structure opposite the first side of the semiconductor structure to which the carrier wafer is directly bonded; and

separating a layer of material from the carrier wafer from a remaining portion of the carrier wafer along the weakened region therein.

2. The method of claim 1, further comprising forming at least one through wafer interconnect (TWI) extending at least partially through the first substrate.

3. The method of claim 1, wherein processing the first semiconductor structure comprises removing a portion of the first substrate from the second side of the first semiconductor structure and exposing at least one conductive structure of the at least a portion of the integrated circuit of the first semiconductor structure.

4. The method of claim 3, wherein exposing at least one conductive structure of the at least a portion of the integrated circuit of the first semiconductor structure comprises exposing a through wafer interconnect (TWI) in the first semiconductor structure.

5. The method of claim 4, wherein directly bonding the second semiconductor structure to the second side of the first semiconductor structure comprises directly bonding the through wafer interconnect of the first semiconductor structure to at least one conductive element of the second semiconductor structure.

6. The method of claim 1, wherein directly bonding the second semiconductor structure to the second side of the first semiconductor structure comprises directly bonding metal of at least one conductive element of the first semiconductor structure to metal of at least one conductive element of the second semiconductor structure.

7. The method of claim 1, wherein directly bonding the second semiconductor structure to the second side of the first semiconductor structure comprises directly bonding at least one of a semiconductor material and an oxide material of the second semiconductor structure to at least one of a semiconductor material and an oxide material of the first semiconductor structure.

8. The method of claim 1, wherein separating the layer of material of the carrier wafer from a remaining portion of the carrier wafer along the weakened region therein comprises annealing the carrier wafer at a temperature of at least 100°

C. and detaching a portion of the carrier wafer overlying the weakened region from another portion of the carrier wafer remaining attached to the first semiconductor structure.

9. The method of claim 1, wherein separating the layer of material from the carrier wafer along the weakened region comprises leaving a layer of material of the carrier wafer having a thickness of between about 10 nm and about 1000 nm attached to the first semiconductor structure.

10. The method of claim 1, wherein the direct bonding of the second semiconductor structure to the second side of the first semiconductor structure results in the separating of the layer of material from the carrier wafer along the weakened region therein.

11. The method of claim 10, wherein the direct bonding of the carrier wafer to the first side of the first semiconductor structure comprises weakening the carrier wafer along the weakened region therein without dividing the carrier wafer along the weakened region therein.

12. A method of fabricating a semiconductor structure, comprising:

implanting ions into a first semiconductor structure and forming a weakened region therein;

directly bonding a surface of the first semiconductor structure to a surface of a second semiconductor structure to form a bonded semiconductor structure including the first semiconductor structure and the second semiconductor structure;

handling the bonded semiconductor structure using the first semiconductor structure while removing a portion of the second semiconductor structure and exposing at least one conductive structure extending at least partially through the second semiconductor structure;

aligning the at least one conductive structure exposed through the second semiconductor structure with at least one conductive structure of a third semiconductor structure;

heating the bonded semiconductor structure and the third semiconductor structure;

directly bonding the at least one conductive structure exposed through the second semiconductor structure to the at least one conductive structure of the third semiconductor structure responsive to heating the bonded semiconductor structure and the third semiconductor structure; and

dividing the first semiconductor structure along the weakened region responsive to heating the bonded semiconductor structure and the third semiconductor structure and leaving a portion of the first semiconductor structure on the second semiconductor structure.

13. The method of claim 12, further comprising forming the at least one conductive structure exposed through the second semiconductor structure to comprise a through wafer interconnect (TWI).

14. The method of claim 12, wherein implanting ions into the first semiconductor structure comprises exposing a surface of a semiconductor wafer to the ions at a dose of between 1×

10¹⁶ ions/cm² and 2×

10¹⁷ ions/cm² and an energy of between 10 KeV and 150 KeV.

15. The method of claim 12, wherein implanting ions into the first semiconductor structure comprises implanting the ions into a carrier wafer and forming a weakened region within the carrier wafer at a depth of between about 10 nm and about 1000 nm from a flat major surface of the carrier wafer.

16. The method of claim 12, wherein directly bonding the surface of the first semiconductor structure to the surface of the second semiconductor structure to form the bonded semiconductor structure comprises bonding a surface of a silicon carrier wafer to a surface of a silicon or a silicon dioxide material of the second semiconductor structure.

17. The method of claim 12, wherein directly bonding the surface of the first semiconductor structure to the surface of the second semiconductor structure to form the bonded semiconductor structure comprises bonding a surface of a silicon dioxide material on a silicon carrier wafer to a surface of a silicon or a silicon dioxide material of the second semiconductor structure.

18. The method of claim 12, wherein aligning the at least one conductive structure exposed through the second semiconductor structure with at least one conductive structure of a third semiconductor structure comprises aligning at least one copper through wafer interconnect (TWI) exposed through the second semiconductor structure with at least one copper bond pad of the third semiconductor structure.

19. The method of claim 12, wherein heating the bonded semiconductor structure and the third semiconductor structure comprises heating the bonded semiconductor structure and the third semiconductor structure to a temperature of between about 100°

C. and about 400°

C.

20. The method of claim 12, further comprising processing the portion of the first semiconductor structure on the second semiconductor structure after dividing the first semiconductor structure along the weakened region and forming at least one device structure on or in the portion of the first semiconductor structure on the second semiconductor structure.

21. The method of claim 12, further comprising removing the portion of the first semiconductor structure from the second semiconductor structure after dividing the first semiconductor structure along the weakened region.

22. A bonded semiconductor structure, comprising:

a plurality of bonded processed semiconductor structures; and

a carrier die or wafer bonded to at least one bonded processed semiconductor structure of the plurality of bonded processed semiconductor structures, the carrier die or wafer having a weakened zone comprising a plurality of implanted ions therein at an average depth of between 10 nm and 1000 nm from a surface of the carrier die or wafer bonded to the at least one bonded processed semiconductor structure of the plurality of bonded processed semiconductor structures.

23. The bonded semiconductor structure of claim 22, wherein the plurality of bonded processed semiconductor structures are structurally and electrically coupled together at least partially by through wafer interconnects.

24. The bonded semiconductor structure of claim 22, wherein the plurality of bonded processed semiconductor structures are directly bonded together without using an adhesive material therebetween.

25. The bonded semiconductor structure of claim 24, wherein the carrier die or wafer is directly bonded to the at least one bonded processed semiconductor structure of the plurality of bonded processed semiconductor structures.