PARALLEL MOTOR DRIVE DISABLE VERIFICATION SYSTEM AND METHOD

• US 20120013284A1
• Filed: 07/16/2010
• Published: 01/19/2012
• Est. Priority Date: 07/16/2010
• Status: Active Grant

• Current Assignee: Rockwell Automation Technologies Incorporated (Allen-Bradley Co., Inc.)
• Original Assignee: Rockwell Automation Technologies Incorporated (Allen-Bradley Co., Inc.)
• Inventors: Campbell, Alan J.
• Granted Patent: US 9,577,424 B2
• Time in Patent Office: Days
• US Class Current: 318/490
• CPC Class Codes: G01R 31/42 AC power supplies
• CPC Class Codes: H02H 7/08 for dynamo-electric motors
• CPC Class Codes: H02P 29/02 Providing protection against overload without automatic interruption of supply protection against faults of stepper motors H02P8/36

Abstract

Systems and methods are provided for performing diagnostic testing for multiple motor drives operating in parallel. In one embodiment, the diagnostic testing may involve determining which of the multiple motor drives are in operation and communicating the active configuration of motor drives to testing circuitry. The testing circuitry generates an enable input signal transmitted to the transistor gates in each of the active motor drives. The testing circuitry also generates a power supply input signal transmitted to a DC to DC converter in each of the active motor drives. The responses to the enable input signal and the power supply input signal are measured to determine safety compliance.

Claims

1. An electric motor drive system comprising:

a plurality of drive modules each comprising a converter for converting incoming AC power to DC power and an inverter coupled to the converter for converting the DC power to controlled frequency AC power;

a common controller coupled to all of the inverters and configured to provide signals to the inverters to permit each inverter to generate gate drive signals for power electronic switches of the respective inverter separately and in parallel with one another; and

shutdown circuitry configured to conduct a shutdown diagnostic test on the plurality of drive modules, wherein the shutdown diagnostic test verifies the ability of the shutdown circuitry to disable to plurality of drive modules.

2. The electric motor drive of claim 1, wherein the shutdown circuitry comprises power layer circuitry in each of the plurality of drive modules, the power layer circuitry of each of the plurality of drive modules being coupled to the common controller via respective optical fiber connections.

3. The electric motor drive of claim 1, wherein the shutdown circuitry is configured to conduct an enable test on each of the plurality of drive modules in parallel, wherein the enable test comprises:

pulsing an enable input signal to transistor gates of the respective one of the plurality of drive modules;

measuring an enable return signal from the transistor gates of the respective one of the plurality of drive modules; and

determining an enable return signal duration for which the enable return signal is at a logic low.

4. The electric motor drive of claim 3, wherein the shutdown circuitry is configured to disable the enable input signal to the transistor gates of the respective one of the plurality of drive modules if the enable return signal duration is greater than time in which the transistor gates switch states.

5. The electric motor drive of claim 3, wherein the shutdown circuitry is configured to disable the enable input signal to the transistor gates of the respective one of the plurality of drive modules if the return signal duration is greater than approximately 5 μ

s.

6. The electric motor drive of claim 3, wherein the shutdown circuitry is configured to conduct a power supply test on each of the plurality of drive modules in parallel, wherein the power supply test comprises:

pulsing a power supply input signal to a DC to DC converter in the respective one of the plurality of drive modules;

measuring a power supply return signal from the DC to DC converter of the respective one of the plurality of drive modules; and

determining a power supply return signal duration for which the enable return signal is at a logic low.

7. The electric motor drive of claim 6, wherein the shutdown circuitry is configured to disable the power supply input signal to the DC to DC converter of the respective one of the plurality of drive modules if the power supply return signal is greater than a threshold.

8. The electric motor drive of claim 7, wherein the threshold is approximately 100 μ

s.

9. The electric motor drive of claim 1, wherein the common controller is configured:

determine an active configuration based on which of the plurality of drive modules is active; and

communicate the active configuration to the shutdown circuitry, wherein the shutdown circuitry is configured to perform the shutdown diagnostic test based on the active configuration.

10. The electric motor drive of claim 1, wherein the common controller is configured to combine feedback from the plurality of drive modules based upon results of the shutdown diagnostic test.

11. The electric motor drive of claim 10, wherein the common controller is configured to shut down at least one of the plurality of drive modules if the at least one of the plurality of drive modules does not return a pass signal as a result of the shutdown diagnostic test.

12. The electric motor drive of claim 11, wherein the common controller is configured to shut down all of the plurality of drive modules if at least one of the plurality of drive modules does not return a pass signal as a result of the shutdown diagnostic test.

13. The electric motor drive of claim 1, wherein the common controller is configured to store data representative of results of the shutdown diagnostic test run by each of the plurality of drive modules.

14. The electric motor drive of claim 1, wherein the common controller is configured to command the shutdown circuitry to run the shutdown diagnostic test periodically during normal operation of the plurality of drive modules in driving an electric motor.

15. The electric motor drive of claim 1, comprising a parallel bus, wherein the plurality of drive modules each comprise a drive interface and the common controller comprises a controller interface, and wherein the parallel bus is configured to connect the controller interface with the drive interface of each of the plurality of drive modules.

16. A method of performing a shutdown diagnostic test in a motor drive, the method comprising:

determining a channel configuration of a plurality of motor drives in the motor drive system, wherein the channel configuration comprises active motor drives in the plurality of motor drives;

communicating the channel configuration to shutdown circuitry;

transmitting a pulsed input signal from the shutdown circuitry in parallel to each of the active motor drives in the channel configuration;

measuring a return signal in parallel from each of the active motor drives;

determining whether the return signal from each of the active motor drives has a logic low period within a threshold; and

deactivating a signal to one of the active motor drives if the return signal does not have a logic low period within the threshold.

17. The method of claim 16, wherein the pulsed input signal comprises a pulsed enable signal transmitted to transistor gates in each of the active motor drives.

18. The method of claim 17, wherein the threshold is based on a switching frequency of the transistor gates.

19. The method of claim 17, wherein the threshold is approximately 5 μ

s.

20. The method of claim 16, wherein the pulsed input signal comprises a pulsed power supply signal transmitted to a DC to DC converter in each of the active motor drives.

21. The method of claim 20, wherein the threshold is approximately 100 μ

s.

22. A method of operating a motor drive, the method comprising:

driving a motor by combined multi-phase output signals from a plurality of parallel inverters;

from common control circuitry coupled to all of the plurality of parallel inverters, transmitting shutdown test signals a shutdown circuitry in a power layer of each of the plurality of inverters in parallel;

receiving in the common control circuitry response data indicative of a result in each power layer of each of the plurality of inverters; and

combining the response data into a single test result value.

23. The method of claim 22, comprising shutting down at least one of the plurality of parallel inverters if the at least one of the plurality of parallel inverters does not return a pass signal as a result of the shutdown diagnostic test.

24. The method of claim 23, comprising shutting down all of the plurality of parallel inverters if at least one of the plurality of parallel inverters does not return a pass signal as a result of the shutdown diagnostic test.

25. The method of claim 22, comprising storing data representative of results of the shutdown diagnostic test run by each of the plurality of parallel inverters.

26. The method of claim 22, comprising running the shutdown diagnostic test periodically during normal operation of the plurality of parallel inverters in driving the electric motor.