Method and System for Wafer Level Testing of Semiconductor Chips

• US 20120013359A1
• Filed: 07/16/2010
• Published: 01/19/2012
• Est. Priority Date: 07/16/2010
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: SHAO, Zhaojun
• Granted Patent: US 9,304,166 B2
• Time in Patent Office: Days
• US Class Current: 324/762.05
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G01R 31/318563 Multiple simultaneous testing of subparts
• CPC Class Codes: H01L 21/00 Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

Abstract

A system and method for wafer level testing of semiconductor chips are provided. In one embodiment, the system comprises a plurality of semiconductor chips disposed in a wafer, each semiconductor chip having at least one port for receiving test data and at least one connection disposed in a kerf region of the wafer between at least one port of a first semiconductor chip and at least one port of at least one second semiconductor chip in the plurality of semiconductor chips, wherein the first semiconductor chip is configured to send the test data to the at least one second semiconductor chip via the at least one connection. Additionally, the plurality of semiconductor chips may comprise at least one core logic configured to pass the test data to the at least one second semiconductor chip via the at least one connection.

Claims

1. A system for testing semiconductor chips comprising:

a plurality of semiconductor chips disposed in a wafer, each of the plurality of semiconductor chips having at least one port for receiving test data;

at least one connection disposed in a kerf region of the wafer between at least one port of a first semiconductor chip and at least one port of at least one second semiconductor chip in the plurality of semiconductor chips,

wherein the first semiconductor chip is configured to send the test data to the at least one second semiconductor chip via the at least one connection.

2. The system of claim 1, wherein the plurality of semiconductor chips are identical to one another.

3. The system of claim 1, wherein the at least one connection comprises:

a first connection disposed in the kerf region between the a first port of the first semiconductor chip and a first port of the at least one second semiconductor chip; and

a second connection disposed in the kerf region between a second port of the first semiconductor chip and a second port of the at least one second semiconductor chip.

4. The system of claim 3, wherein the first semiconductor chip is configured to send the test data to the at least one second semiconductor chip via the first connection and the second connection simultaneously.

5. The system of claim 1, wherein the at least one port of the plurality of semiconductor chips comprises at least one test input port and at least one test output port.

6. The system of claim 5, further comprising:

an automated test equipment comprising;

at least one channel coupled to the at least one test input port of the first semiconductor chip; and

at least one channel coupled to at least one test output port of the plurality of semiconductor chips.

7. The system of claim 6, wherein the first semiconductor chip is configured to receive the test data from the at least one channel of the automated test equipment at the at least one test input port of the first semiconductor chip.

8. The system of claim 7, wherein the first semiconductor is configured to send the test data received at the at least one test input port to the at least one test input port of the at least one second semiconductor chip via the at least one connection.

9. A method for testing semiconductor chips comprising:

providing a plurality of semiconductor chips in a wafer;

connecting at least one port of the plurality of semiconductor chips via at least one connection in a kerf region of the wafer;

sending test data from a tester to the at least one port of a first semiconductor chip in the plurality of semiconductor chips; and

passing the test data from the at least one port of the first semiconductor chip to at least one port of at least one second semiconductor chip via the at least one connection.

10. The method of claim 9, wherein connecting at least one port of the plurality of semiconductor chips via at least one connection in a kerf region of the wafer comprises:

connecting a first port of the first semiconductor chip to a first port of the at least one second semiconductor chip via a first connection in the kerf region; and

connecting a second port of the first semiconductor chip to a second port of the at least one second semiconductor chip via a second connection in the kerf region.

11. The method of claim 10, wherein the first port and the second port are at least one test input port for receiving the test data.

12. The method of claim 10, wherein passing the test data from the at least one port of the first semiconductor chip to at least one port of at least one second semiconductor chip via the at least one connection comprises:

receiving the test data from at least one channel of the tester at the first port and the second port of the first semiconductor chip; and

sending the test data to the first port and the second port of the at least one second semiconductor chip via the first connection and second connection simultaneously.

13. A system for testing semiconductor chips comprising:

a plurality of semiconductor chips disposed in a wafer, each of the plurality of semiconductor chips having at least one port for receiving test data and at least one core logic;

at least one connection disposed in a kerf region of the wafer between at least one port of a first semiconductor chip and at least one port of at least one second semiconductor chip in the plurality of semiconductor chips,

wherein the core logic of the first semiconductor chip is configured to pass the test data to the at least one second semiconductor chip via the at least one connection.

14. The system of claim 13, wherein the at least one port of the first semiconductor chip comprises:

a first set of ports coupled to a tester; and

a second set of ports coupled to the at least one port of the at least one second semiconductor chip via the at least one connection.

15. The system of claim 14, wherein the core logic of the first semiconductor chip is configured to connect the first set of ports with the second set of ports via at least one internal path.

16. The system of claim 14, wherein the core logic of the first semiconductor chip is configured to pass the test data from the second set of ports to the at least one port of the at least one second semiconductor chip via the at least one connection.

17. The system of claim 14, wherein the second set of ports are coupled to at least one port of a second semiconductor chip of the at least one second semiconductor chip and at least one port of a third semiconductor chip of the at least one second semiconductor chip.

18. The system of claim 17, wherein the core logic of the first semiconductor chip is configured to pass the test data from the second set of ports to at least one port of the second semiconductor chip via a first subset of the at least one connection, and to at least one port of the third semiconductor chip via a second subset of the at least one connection.

19. The system of claim 13, wherein the at least one port of the first semiconductor chip comprises:

a first set of ports coupled to a tester; and

a second set of ports coupled to the at least one port of a second semiconductor chip in the at least one second semiconductor chip via a first subset of the at least one connection; and

a third set of ports coupled to the at least one port of a third semiconductor chip in the at least one second semiconductor chip via a second subset of the at least one connection.

20. The system of claim 19, wherein the core logic is configured to pass the test data from the second set of ports to at least one port of the second semiconductor chip via the first subset of the at least one connection, and from the third set of ports to at least one port of the third semiconductor chip via a second subset of the at least one connection.

21. A method for testing semiconductor chips comprising:

providing a plurality of semiconductor chips in a wafer;

configuring at least one core logic to control the plurality of semiconductor chips;

connecting at least one port of the plurality of semiconductor chips via at least one connection in a kerf region of the wafer; and

sending test data from a tester to the at least one port of a first semiconductor chip in the plurality of semiconductor chips; and

passing the test data from the at least one port of the first semiconductor chip to at least one port of at least one second semiconductor chip via the at least one connection.

22. The method of claim 21, wherein configuring the at least one core logic to control the plurality of semiconductor chips comprises:

configuring the core logic to connect a first set of ports of the first semiconductor chip to a second set of ports of the first semiconductor chip upon the first semiconductor chip entering a test mode.

23. The method of claim 22, wherein sending test data from a tester to the at least one port of a first semiconductor chip in the plurality of semiconductor chips comprises:

receiving the test data from at least one channel of the tester at the first set of ports of the first semiconductor chip; and

sending the test data from the first set of ports to the second set of ports of the first semiconductor chip via at least one internal path.

24. The method of claim 22, wherein connecting at least one port of the plurality of semiconductor chips via at least one connection in a kerf region of the wafer comprises:

connecting the second set of ports of the first semiconductor chip to at least one port of a second semiconductor chip of the at least one second semiconductor chip via a first subset of the at least one connection; and

connecting the second set of ports of the first semiconductor chip to at least one port of a third semiconductor chip of the at least one second semiconductor chip via a second subset of the at least one connection.

25. The method of claim 24, wherein passing the test data from the at least one port of the first semiconductor chip to at least one port of at least one second semiconductor chip via the at least one connection comprises:

sending the test data from the second set of ports of the first semiconductor chip to at least one port of the second semiconductor chip of the at least one second semiconductor chip via the first subset of the at least one connection; and

sending the test data from the second set of ports of the first semiconductor chip to at least one port of the third semiconductor chip of the at least one second semiconductor chip via the second subset of the at least one connection simultaneously.

26. The method of claim 22, wherein configuring at least one core logic to control the plurality of semiconductor chips further comprises:

configuring the core logic to connect a third set of ports of the first semiconductor chip upon the first semiconductor chip entering a test mode.

27. The method of claim 26, wherein connecting at least one port of the plurality of semiconductor chips via at least one connection in a kerf region of the wafer comprises:

connecting the second set of ports of the first semiconductor chip to at least one port of a second semiconductor chip of the at least one second semiconductor chip via a first subset of the at least one connection; and

connecting the third set of ports of the first semiconductor chip to at least one port of a third semiconductor chip of the at least one second semiconductor chip via a second subset of the at least one connection.

28. The method of claim 27, wherein passing the test data from the at least one port of the first semiconductor chip to at least one port of at least one second semiconductor chip via the at least one connection comprises:

sending the test data from the second set of ports of the first semiconductor chip to at least one port of the second semiconductor chip of the at least one second semiconductor chip via the first subset of the at least one connection; and

sending the test data from the third set of ports of the first semiconductor chip to at least one port of the third semiconductor chip of the at least one second semiconductor chip via the second subset of the at least one connection simultaneously.