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Method and System for Wafer Level Testing of Semiconductor Chips

  • US 20120013359A1
  • Filed: 07/16/2010
  • Published: 01/19/2012
  • Est. Priority Date: 07/16/2010
  • Status: Active Grant
First Claim
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1. A system for testing semiconductor chips comprising:

  • a plurality of semiconductor chips disposed in a wafer, each of the plurality of semiconductor chips having at least one port for receiving test data;

    at least one connection disposed in a kerf region of the wafer between at least one port of a first semiconductor chip and at least one port of at least one second semiconductor chip in the plurality of semiconductor chips,wherein the first semiconductor chip is configured to send the test data to the at least one second semiconductor chip via the at least one connection.

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