CORRECTION SIGNAL GENERATOR AND ANALOG-TO-DIGITAL CONVERTER

• US 20120013493A1
• Filed: 09/23/2011
• Published: 01/19/2012
• Est. Priority Date: 03/30/2009
• Status: Active Grant

• Current Assignee: DENSO Corporation, Olympus Corporation
• Original Assignee: Olympus Corporation
• Inventors: Kato, Shuichi
• Granted Patent: US 8,581,767 B2
• Time in Patent Office: Days
• US Class Current: 341/120
• CPC Class Codes: H03M 1/0619 by dividing out the errors, i.e. using a ratiometric arrangement
• CPC Class Codes: H03M 1/502 using tapped delay lines
• CPC Class Codes: H03M 1/60 with intermediate conversion to frequency of pulses

Abstract

A correction signal generator generates a correction signal that corrects a digital signal obtained from an analog input voltage. The correction signal generator has a correction signal output circuit that holds the number of transit stages of delay units detected by a first stage count detection circuit and a third stage count detection circuit at the timing corresponding to the difference in the number of stages between the number of transit stages of delay units detected by the first stage count detection circuit and the number of transit stages of delay units detected by a second stage count detection circuit, and outputs the difference between the number of stages from the first stage count detection circuit and the number of stages from the third stage count detection circuit, which were held, as the correction signal.

Claims

1. A correction signal generator that generates a correction signal that corrects a digital signal obtained from an analog input voltage, the correction signal generator comprising:

a first stage number detection circuit including a first pulse delay circuit and a first pulse passage stage number detection circuit, a plurality of stages of delay units each of which delays a first pulse signal by a delay time corresponding to a magnitude of the analog input voltage being connected in the first pulse delay circuit, the first pulse passage stage number detection circuit detecting the number of stages of delay units in the first pulse delay circuit through which the first pulse signal has passed;

a level shift circuit configured to output an analog voltage obtained by shifting a voltage level of the analog input voltage;

a second stage number detection circuit including a second pulse delay circuit and a second pulse passage stage number detection circuit, a plurality of stages of delay units that delays a second pulse signal by a delay time corresponding to a magnitude of the analog voltage with the voltage level shifted by the level shift circuit being connected in the second pulse delay circuit, the second pulse passage stage number detection circuit detecting the number of stages of delay units in the second pulse delay circuit through which the second pulse signal has passed;

a third stage number detection circuit including a third pulse delay circuit and a third pulse passage stage number detection circuit, a plurality of stages of delay units that delays a third pulse signal by a delay time corresponding to a magnitude of a first analog reference voltage, which is a first prescribed voltage value, being connected in the third pulse delay circuit, the third pulse passage stage number detection circuit detecting the number of stages of delay units in the third pulse delay circuit through which the third pulse signal has passed; and

a correction signal output circuit configured to retain the number of passage stages of delay units detected by the first stage number detection circuit and the third stage number detection circuit at a timing corresponding to a stage number difference between the number of passage stages of delay units detected by the first stage number detection circuit and the number of passage stages of delay units detected by the second stage number detection circuit, the correction signal output circuit outputting a difference between the number of stages from the first stage number detection circuit and the number of stages from the third stage number detection circuit retained as a correction signal.

2. The correction signal generator according to claim 1, wherein the correction signal output circuit retains the number of stages of delay units detected by the first stage number detection circuit at a timing when the stage number difference between the number of passage stages of delay units detected by the first stage number detection circuit and the number of passage stages of delay units detected by the second stage number detection circuit becomes a prescribed stage number difference.

3. An analog-to-digital (A/D) converter that converts an analog input voltage into a digital signal, the A/D converter comprising:

a fourth stage number detection circuit including a fourth pulse delay circuit and a fourth pulse passage stage number detection circuit, a plurality of stages of delay units that delays a fourth pulse signal by a delay time corresponding to a magnitude of the analog input voltage being connected in the fourth pulse delay circuit, the fourth pulse passage stage number detection circuit detecting the number of stages of delay units in the fourth pulse delay circuit through which the fourth pulse signal has passed in a predetermined time;

a fifth stage number detection circuit including a fifth pulse delay circuit and a fifth pulse passage stage number detection circuit, a plurality of stages of delay units that delays a fifth pulse signal by a delay time corresponding to a magnitude of a second analog reference voltage, which is a prescribed second voltage value, being connected in the fifth pulse delay circuit, the fifth pulse passage stage number detection circuit detecting the number of stages of delay units in the fifth pulse delay circuit through which the fifth pulse signal has passed in the predetermined time;

an output circuit configured to subtract the number of passage stages of delay units detected by the fifth stage number detection circuit from the number of passage stages of delay units detected by the fourth stage number detection unit, the output circuit outputting a subtraction result of the number of passage stages of delay units as a digital signal;

the correction signal generator according to claim 1; and

a correction circuit configured to correct a digital signal output from the output circuit based on the correction signal output from the correction signal generator and outputting the corrected digital signal.

4. The A/D converter according to claim 3, wherein the correction circuit averages the correction signal output from the correction signal generator and the digital signal output from the output circuit, and outputs an averaged digital signal.

5. The A/D converter according to claim 3, wherein the second analog reference voltage is equal to the first analog reference voltage.

6. The A/D converter according to claim 3, further comprising:

a timer circuit configured to set the predetermined time so that the number of passage stages of delay units detected by the fifth stage number detection circuit is substantially equal to the number of stages from the third stage number detection circuit retained by the correction signal output circuit if the second analog reference voltage is equal to the first analog reference voltage and the analog input voltage.