DYNAMIC CONTROL OF SIMDs

• US 20120013627A1
• Filed: 07/12/2011
• Published: 01/19/2012
• Est. Priority Date: 07/13/2010
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Mantor, Michael J., Emberling, Brian, Shah, Tushar K.
• Granted Patent: US 9,311,102 B2
• Time in Patent Office: Days
• US Class Current: 345/522
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems and methods to improve performance in a graphics processing unit are described herein. Embodiments achieve power saving in a graphics processing unit by dynamically activating/deactivating individual SIMDs in a shader complex that comprises multiple SIMD units. On-the-fly dynamic disabling and enabling of individual SIMDs provides flexibility in achieving a required performance and power level for a given processing application. Embodiments of the invention also achieve dynamic medium grain clock gating of SIMDs in a shader complex. Embodiments reduce switching power by shutting down clock trees to unused logic by providing a clock on demand mechanism. In this way, embodiments enhance clock gating to save more switching power for the duration of time when SIMDs are idle (or assigned no work). Embodiments can also save leakage power by power gating SIMDs for a duration when SIMDs are idle for an extended period of time.

Claims

1. A method improve performance in a computing system, comprising:

determining a required power level for a processing application; and

dynamically enabling and disabling one or more single instruction multiple data units (SIMDs) in a shader complex based on said power level.

2. The method of claim 1, further comprising:

configuring, in real-time, a plurality of registers to indicate when said SIMDs are to be enabled and disabled.

3. The method of claim 1, further comprising:

determining a number of SIMDs needed for said processing application.

4. The method of claim 2, further comprising:

reviewing said configured registers; and

assigning work threads based on configuration of said registers.

5. The method of claim 2, further comprising:

servicing one or more pending work requests prior to said configuring.

6. The method of claim 1, wherein said dynamically enabling and disabling comprises enabling and disabling said SIMDs during their active execution period and independent of activity in a shader engine associated with said SIMDs.

7. The method of claim 2, further comprising:

disabling work threads to one or more SIMDs that are to be disabled; and

determining when all pending work threads in said to-be-disabled SIMDs are cleared.

8. The method of claim 1, wherein said enabling and disabling is dependent on one or more of processing work load, application requirements and operating conditions.

9. The method of claim 1, further comprising providing dynamic medium grain clock gating to said SIMDs.

10. The method of claim 9, further comprising disabling clock trees to unused logic in said SIMDs.

11. The method of claim 1, further comprising providing clocking on demand to said SIMDs.

12. A system to improve performance in a computing system, comprising:

a first module configured to determine a power level for a processing application; and

a second module configured to dynamically enable and disable one or more single instruction multiple data units (SIMDs) in a shader complex based on said power level.

13. The system of claim 12, wherein said second module configures, in real-time, a plurality of registers to indicate when said SIMDs are to be enabled and disabled.

14. The system for claim 13, wherein said second module is further configured to:

review said configured registers; and

assign work threads based on configuration of said registers.

15. The system of claim 13, wherein said second module services one or more pending work requests prior to said configuring.

16. The system of claim 12, wherein said second module is further configured to enable and disable said SIMDs during their active execution period and independent of activity in a shader engine associated with said SIMDs.

17. A computer-readable medium that stores instructions adapted to be executed by a

processor to:

determinine a required power level for a processing application; and

dynamically enable and disable one or more single instruction multiple data units (SIMDs) in a shader complex based on said power level.

18. The computer-readable medium of claim 17, further comprising instructions adapted to be executed by the processor to:

configure, in real-time, a plurality of registers to indicate when said SIMDs are to be enabled and disabled.

19. The computer-readable medium of claim 17, further comprising instructions adapted to be executed by the processor to:

determine a number of SIMDs needed for said processing application.

20. The computer-readable medium of claim 18, further comprising instructions adapted to be executed by the processor to:

review said configured registers; and

assign work threads based on configuration of said registers.