SEMICONDUCTOR DEVICE

• US 20120014157A1
• Filed: 07/01/2011
• Published: 01/19/2012
• Est. Priority Date: 07/16/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kato, Kiyoshi, Matsuzaki, Takanori, Inoue, Hiroki, Nagatsuka, Shuhei
• Granted Patent: US 8,576,636 B2
• Time in Patent Office: Days
• US Class Current: 365/72
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A plurality of memory cells included in a memory cell array are divided into a plurality of blocks every plural rows. A common bit line is electrically connected to the divided bit lines through selection transistors in the blocks. One of the memory cells includes a first transistor, a second transistor, and a capacitor. The first transistor includes a first channel formation region. The second transistor includes a second channel formation region. The first channel formation region includes a semiconductor material different from the semiconductor material of the second channel formation region.

Claims

1. A semiconductor device comprising:

a common bit line;

a plurality of divided bit lines electrically connected to the common bit line;

a source line;

a word line;

a signal line;

a selection line;

a selection transistor whose gate is electrically connected to the selection line;

a plurality of memory cell arrays divided into a plurality of blocks every plural rows; and

a plurality of memory cells included in each of the plurality of memory cell arrays, one of the plurality of memory cells in one of the plurality of memory cell arrays comprising;

a first transistor including a first gate, a first source, a first drain, and a first channel formation region;

a second transistor including a second gate, a second source, a second drain, and a second channel formation region; and

a capacitor,

wherein the common bit line is electrically connected to a first divided bit line of the plurality of divided bit lines through the selection transistor,

wherein the source line is electrically connected to the first source,

wherein the first divided bit line is electrically connected to the first drain and the second source,

wherein the word line is electrically connected to one electrode of the capacitor,

wherein the signal line is electrically connected to the second gate, and

wherein the first gate, the second drain, and the other electrode of the capacitor are electrically connected to each other.

2. The semiconductor device according to claim 1, wherein the second channel formation region includes an oxide semiconductor.

3. The semiconductor device according to claim 1, wherein the first channel formation region includes single crystal silicon.

4. The semiconductor device according to claim 1, wherein a channel formation region of the selection transistor includes single crystal silicon.

5. A semiconductor device comprising:

a common bit line;

a plurality of divided bit lines electrically connected to the common bit line;

a source line;

a word line;

a first signal line;

a second signal line;

a selection line;

a selection transistor whose gate is electrically connected to the selection line;

a plurality of memory cell arrays divided into a plurality of blocks every plural rows; and

a plurality of memory cells included in each of the plurality of memory cell arrays, one of the plurality of memory cells in one of the plurality of memory cell arrays comprising;

a first transistor including a first gate, a first source, a first drain, and a first channel formation region;

a second transistor including a second gate, a second source, a second drain, and a second channel formation region; and

a capacitor,

wherein the common bit line is electrically connected to a first divided bit line of the plurality of divided bit lines through the selection transistor,

wherein the source line is electrically connected to the first source,

wherein the first divided bit line is electrically connected to the first drain,

wherein the word line is electrically connected to one electrode of the capacitor,

wherein the first signal line is electrically connected to the second gate,

wherein the second signal line is electrically connected to the second source, and

wherein the first gate, the second drain, and the other electrode of the capacitor are electrically connected to each other.

6. The semiconductor device according to claim 5, wherein the second channel formation region includes an oxide semiconductor.

7. The semiconductor device according to claim 5, wherein the first channel formation region includes single crystal silicon.

8. The semiconductor device according to claim 5, wherein a channel formation region of the selection transistor includes single crystal silicon.

9. A semiconductor device comprising:

a first bit line;

a second bit line electrically connected to the first bit line through a first selection transistor;

a plurality of first memory cells each electrically connected to the second bit line;

a third bit line electrically connected to the first bit line through a second selection transistor; and

a plurality of second memory cells each electrically connected to the third bit line;

each of the plurality of first memory cells comprising;

a first transistor comprising a gate, a source, and a drain, wherein the source of the first transistor is electrically connected to a source line, and the drain of the first transistor is electrically connected to the second bit line;

a second transistor comprising a gate, a source, and a drain, wherein the source of the second transistor is electrically connected to the second bit line, and the gate of the second transistor is electrically connected to a first signal line; and

a first capacitor comprising a first electrode and a second electrode, wherein the first electrode of the first capacitor is electrically connected to the gate of the first transistor and the drain of the second transistor, and the second electrode of the first capacitor is electrically connected to a first word line;

each of the plurality of second memory cells comprising;

a third transistor comprising a gate, a source, and a drain, wherein the source of the third transistor is electrically connected to the source line, and the drain of the third transistor is electrically connected to the third bit line;

a fourth transistor comprising a gate, a source, and a drain, wherein the source of the fourth transistor is electrically connected to the third bit line, and the gate of the fourth transistor is electrically connected to a second signal line; and

a second capacitor comprising a first electrode and a second electrode, wherein the first electrode of the second capacitor is electrically connected to the gate of the third transistor and the drain of the fourth transistor, and the second electrode of the second capacitor is electrically connected to a second word line.

10. The semiconductor device according to claim 9, wherein a channel formation region of the second transistor includes an oxide semiconductor.

11. The semiconductor device according to claim 9, wherein a channel formation region of the first transistor includes single crystal silicon.

12. The semiconductor device according to claim 9, wherein a channel formation region of the first selection transistor and a channel formation region of the second selection transistor include single crystal silicon.