Method of fabricating a high-voltage transistor with an extended drain structure

• US 20120015491A1
• Filed: 08/12/2011
• Published: 01/19/2012
• Est. Priority Date: 09/07/2001
• Status: Active Grant

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Disney, Donald Ray
• Granted Patent: US 8,940,605 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: Y10S 438/925 Fluid growth doping control, e.g. delta doping

Abstract

A method for fabricating a high-voltage transistor with an extended drain region includes forming in a semiconductor substrate of a first conductivity type, first and second trenches that define a mesa having respective first and second sidewalls; then partially filling each of the trenches with a dielectric material that covers the first and second sidewalls. The remaining portions of the trenches are then filled with a conductive material to form first and second field plates. Source and body regions are formed in an upper portion of the mesa, with the body region separating the source from a lower portion of the mesa. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

Claims

1. -33. (canceled)

34. A method comprising:

forming, in a semiconductor substrate of a first conductivity type, first and second trenches that define a mesa having respective first and second sidewalls, the mesa being formed with a doping concentration that is lower near the body region, as compared to the lower portion;

covering the first and second sidewalls of each of the trenches with a dielectric material;

forming first and second field plates in the first and second trenches, respectively, the first and second field plates extending vertically from a top surface of the semiconductor substrate down to near a bottom of the mesa;

forming source and body regions in an upper portion of the mesa, the source region being of the first conductivity type and the body region being of a second conductivity type opposite to the first conductivity type, the body region separating the source region from a lower portion of the mesa, the lower portion of the mesa comprising a drift region, the dielectric material and the field plates being formed with a reduced spacing between the field plates and the mesa near the body region as compared to near the lower portion of the mesa; and

forming a trench gate within the dielectric material adjacent the body region, the trench gate being insulated from the body region and the first and second field plates.

35. The method of claim 34 further comprising:

forming a drain region of the first conductivity type at the bottom of the mesa, the drain region being connected to the drift region; and

forming a drain electrode connected to the substrate.

36. The method of claim 34 wherein the first conductivity type is n-type.

37. The method of claim 34 wherein the mesa is formed with a doping concentration that is lower near the body region, as compared to the lower portion.

38. The method of claim 34 wherein the drift region has a linearly graded doping profile.

39. The method of claim 35 further comprising forming a source electrode electrically coupled to the source region.

40. The method of claim 39 wherein the source electrode is also electrically coupled to the first and second field plates.

41. A method for fabricating a power transistor comprising:

forming an epitaxial layer of a first conductivity type on a substrate, the epitaxial layer being formed with a linearly graded doping profile;

forming first and second trenches in the epitaxial layer that defines a mesa, the mesa having first and second sidewalls.

covering the first and second sidewalls with a dielectric material;

forming first and second field plates in the first and second trenches, respectively, the first and second field plates extending vertically from a top surface of the semiconductor substrate down to near a bottom of the mesa;

forming source and body regions in an upper portion of the mesa, the source region being of the first conductivity type and the body region being of a second conductivity type opposite to the first conductivity type, the body region separating the source from a lower portion of the mesa, the lower portion of the mesa comprising a drift region, the dielectric material and the field plates being formed with a reduced spacing between the field plates and the mesa near the body region as compared to near the lower portion of the mesa; and

forming a trench gate within the dielectric material adjacent the body region, the trench gate being insulated from the body region and the first and second field plates.

42. The method of claim 41 wherein the substrate is of the first conductivity type.

43. The method of claim 41 further comprising:

forming a drain region of the first conductivity type at the bottom of the mesa, the drain region being connected to the drift region; and

forming a drain electrode connected to the substrate.

44. The method of claim 41 wherein the first conductivity type is n-type.

45. The method of claim 42 wherein the mesa is formed with a doping concentration that is lower near the body region, as compared to the lower portion.

46. The method of claim 45 wherein the substrate has a higher doping concentration than the lower portion of the mesa.

47. The method of claim 43 further comprising forming a source electrode electrically coupled to the source region.

48. The method of claim 47 wherein the source electrode is also electrically coupled to the first and second field plates.