CACHING USING VIRTUAL MEMORY

• US 20120017039A1
• Filed: 07/16/2010
• Published: 01/19/2012
• Est. Priority Date: 07/16/2010
• Status: Abandoned Application

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: PLX Technology Incorporated (Broadcom, Inc.)
• Inventors: MARGETTS, Julien
• Application Number:
  US12/837,778
• Publication Number:
  US 20120017039A1
• Time in Patent Office: Days
• US Class Current: 711/105
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/122 of the least frequently used [LFU] type, e.g. with individual count value
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory

Abstract

In a first embodiment of the present invention, a method for caching in a processor system having virtual memory is provided, the method comprising: monitoring slow memory in the processor system to determine frequently accessed pages; for a frequently accessed page in slow memory: copy the frequently accessed page from slow memory to a location in fast memory; and update virtual address page tables to reflect the location of the frequently accessed page in fast memory.

Claims

1. A method for caching in a processor system having virtual memory, the method comprising:

monitoring slow memory in the processor system to determine frequently accessed pages;

for a frequently accessed page in slow memory;

copying the frequently accessed page from slow memory to a location in fast memory; and

updating virtual address page tables to reflect the location of the frequently accessed page in fast memory.

2. The method of claim 1, wherein the slow memory is Dynamic Random Access Memory (DRAM).

3. The method of claim 1, wherein the fast memory is Static Random Access Memory (SRAM).

4. The method of claim 1, further comprising:

receiving a command requiring information;

determining if the information is contained in a level 1 cache;

if the information is not contained in the level 1 cache;

accessing a virtual address page table to determine a physical location for the information;

retrieving the information from slow memory if the location for the information indicates it is in slow memory; and

retrieving the information from fast memory if the location for the information indicates it is in fast memory.

5. The method of claim 1, wherein the monitoring includes repeatedly scanning pages of memory corresponding to a predetermined range of addresses in slow memory sequentially.

6. The method of claim 1, wherein a page is determined to be frequently accessed based upon the number of accesses counted for the page during a predetermined period of time.

7. A method for operating a processor contained on a microchip, the method comprising:

receiving a command requiring information stored in a memory page;

determining if the information is located in a level 1 cache stored on the microchip;

retrieving the information from the level 1 cache if the information is located in the level 1 cache, otherwise;

accessing page tables controlled by a virtual memory management unit on the microchip, to determine a location for the memory page;

retrieving the information from a slow memory external to the microchip if the page tables indicate that the memory page is located in the slow memory; and

retrieving the information from a fast memory on the microchip if the page tables indicate that the page is located in the fast memory;

continuously monitoring the slow memory to locate heavily accessed pages; and

copying heavily accessed pages from the slow memory to the fast memory and updating the pages tables to reflect the locations of the heavily accessed pages in fast memory.

8. The method of claim 7, wherein the method is performed in hardware.

9. The method of claim 7, wherein the method is performed as a software process separate from the processor.

10. The method of claim 7, wherein the method is performed as a task of the processor.

11. The method of claim 7, wherein the continuously monitoring and copying heavily accessed pages includes only copying heavily accessed static pages while leaving heavily accessed dynamic pages untouched.

12. A microchip comprising:

a processor;

a virtual memory address translation unit;

a first memory storing page tables controlled by the virtual memory address translation unit;

a second memory storing a level 1 cache;

a third memory comprising fast memory;

a system bus interface configured to interface with a system bus connected to a fourth memory, wherein the fourth memory comprises slow memory; and

wherein the virtual memory address translation unit is configured to, upon a notification of a level 1 cache miss, access the page tables in the first memory to determine if a location of a page corresponding to the level 1 cache miss is contained in the third memory or the fourth memory, and to return the corresponding location to the processor for retrieval.

13. The microchip of claim 12, wherein the third memory is four times as large as the second cache.

14. The microchip of claim 12, wherein the third memory is large enough to fit at least eight pages.

15. A program storage device readable by a machine tangibly embodying a program of instructions executable by the machine to perform a method for operating a processor contained on a microchip, the method comprising:

receiving a command requiring information stored in a memory page;

determining if the information is located in a level 1 cache stored on the microchip;

retrieving the information from the level 1 cache if the information is located in the level 1 cache, otherwise;

accessing page tables controlled by a virtual memory management unit on the microchip, to determine a location for the memory page;

retrieving the information from a slow memory external to the microchip if the page tables indicate the memory page is located in the slow memory; and

retrieving the information from a fast memory on the microchip if the page tables indicate the page is located in the fast memory;

continuously monitoring the slow memory to locate heavily accessed pages; and

copying heavily accessed pages from the slow memory to the fast memory and updating the pages tables to reflect the locations of the heavily accessed pages in fast memory.

16. The program storage device of claim 15, wherein the continuously monitoring and copying heavily accessed pages includes only copying heavily accessed static pages while leaving heavily accessed dynamic pages untouched.

17. The program storage device of claim 15, wherein the continuously monitoring includes repeatedly scanning cache lines corresponding to a predetermined range of addresses in slow memory sequentially.

18. The program storage device of claim 15, wherein a page is determined to be frequently accessed based upon the number of accesses counted for the page during a predetermined period of time.

19. The program storage device of claim 15, wherein the slow memory is Dynamic Random Access Memory (DRAM).

20. The program storage device of claim 15, wherein the fast memory is Static Random Access Memory (SRAM).