NONVOLATILE MEMORY APPARATUS FOR PERFORMING WEAR-LEVELING AND METHOD FOR CONTROLLING THE SAME

• US 20120017053A1
• Filed: 12/08/2010
• Published: 01/19/2012
• Est. Priority Date: 07/15/2010
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: YANG, Wun Mo, Liu, Yi Chun
• Granted Patent: US 8,671,239 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7211 Wear leveling

Abstract

Various embodiments of a nonvolatile memory apparatus are disclosed. In one exemplary embodiment, the nonvolatile memory apparatus may include: a host interface; a memory controller coupled to the host interface; and a memory area including a plurality of chips controlled by the memory controller. The memory controller may be configured to assign logical addresses to the plurality of chips to form a plurality of virtual logical groups, set a plurality of threshold values and a plurality of scan ranges depending on the total erase count (TEC) of each logical group, and perform wear-leveling in stages.

Claims

1. A nonvolatile memory apparatus comprising:

a host interface;

a memory controller coupled to the host interface; and

a memory area comprising a plurality of chips controlled by the memory controller,

wherein the memory controller is configured to assign logical addresses to the plurality of chips to form a plurality of virtual logical groups, set a plurality of threshold values and a plurality of scan ranges depending on a total erase count (TEC) of each logical group, and perform wear-leveling in a stepwise manner.

2. The nonvolatile memory apparatus according to claim 1, wherein the memory controller stores deviation information among erase counts (EC) of chips that are included in different logical groups but physically correspond to the same channel.

3. The nonvolatile memory apparatus according to claim 2, wherein the memory controller is configured to set a target logical group on which wear-leveling is to be performed by using the TEC of each logical group, and trace a target chip within the target logical group by using the deviation information.

4. The nonvolatile memory apparatus according to claim 3, wherein, when the target logical group is set, the memory controller is configured to control the scan range of chips included in the corresponding logical group to vary according to a threshold value of the logical group.

5. The nonvolatile memory apparatus according to claim 4, wherein, as the threshold value of the logical group increases, the memory controller controls the scan range of the chip included in the corresponding logical group to be extended.

6. The nonvolatile memory apparatus according to claim 1, wherein the memory controller is configured to accumulate and store the TEC of chips that are included in different logical groups but physically correspond to the same channel.

7. A nonvolatile memory apparatus comprising:

a host interface;

a memory controller coupled to the host interface; and

a memory area comprising a plurality of chips controlled by the memory controller,

wherein the memory controller is configured to group the plurality of chips into a plurality of virtual logical groups, and perform wear-leveling by using TEC information of each logical group and EC information of chips physically corresponding to the same channel.

8. The nonvolatile memory apparatus according to claim 7, wherein the memory controller is configured to store the TEC of each logical group by accumulating the ECs of chips within the logical group.

9. The nonvolatile memory apparatus according to claim 8, wherein the memory controller is configured to set a target logical group on which wear-leveling is to be performed by using the TEC of each logical group.

10. The nonvolatile memory apparatus according to claim 9, wherein, when the target logical group is set, the memory controller is configured to control the scan range of chips included in the corresponding logical group to vary according to the TEC of the logical group.

11. The nonvolatile memory apparatus according to claim 10, wherein, as the TEC of the logical group increases, the memory controller is configured to control the scan range of the chips included in the corresponding logical group to be extended.

12. The nonvolatile memory apparatus according to claim 7, wherein the memory controller is configured to store the EC deviation information among chips that are included in different logical groups but physically correspond to the same channel.

13. The nonvolatile memory apparatus according to claim 12, wherein the memory controller is configured to trace a target chip within the target logical group on which wear-leveling is to be performed by using the deviation information.

14. The nonvolatile memory apparatus according to claim 7, wherein the memory controller is configured to individually accumulate the ECs of chips that are included in different logical groups but physically correspond to the same channel, and store the accumulated value for each chip.

15. The nonvolatile memory apparatus according to claim 14, wherein the memory controller is configured to trace a target chip within the target logical group on which wear-leveling is to be performed by using the accumulated value for each chip.

16. A method for controlling a nonvolatile memory apparatus, comprising:

accumulating a TEC of each virtual logical group comprising a plurality of chips;

storing deviation information among the respective chips by using ECs of the chips;

when a wear-leveling condition is met, determining whether the TEC of the logical group exceeds one of a plurality of predetermined threshold values; and

differently defining a chip scan range of a target logical group on which wear-leveling is to be performed, depending on a determination result.

17. The method according to claim 16, wherein the target logical group is set by using the TEC.

18. The method according to claim 16, wherein the ECs of the chips are used to trace a target chip within the defined chip scan range.

19. The method according to claim 18, wherein, when the target chip is traced, wear-leveling is performed by substituting the logical address of the target chip with that of a chip having the smallest EC within the defined chip scan range.

20. The method according to claim 16, wherein determining is to comprises determining, sequentially one after another, whether the TEC of the logical group exceeds any of the plurality of predetermined threshold values.