LOW LATENCY MASSIVE PARALLEL DATA PROCESSING DEVICE

• US 20120017066A1
• Filed: 02/14/2011
• Published: 01/19/2012
• Est. Priority Date: 07/24/2003
• Status: Abandoned Application

• Current Assignee: Frank Mayer, Martin Vorbach
• Original Assignee: Frank Mayer, Martin Vorbach
• Inventors: Vorbach, Martin, May, Frank
• Application Number:
  US13/026,475
• Publication Number:
  US 20120017066A1
• Time in Patent Office: Days
• US Class Current: 712/11
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30058 Conditional branch instructions
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead
• CPC Class Codes: G06F 9/3842 Speculative instruction execution
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

Data processing device comprising a multidimensional array of ALUs, having at least two dimension where the number of ALUs in the dimension is greater or equal to 2, adapted to process data without register caused latency between at least some of the ALUs in the corresponding array.

Claims

1-6. -6. (canceled)

7. A programmable chip for processing video, comprising:

at least one control processor that is programmable at a hardware level;

at least one second processor for processing at least one of context-adaptive variable-length coding (CAVLC), context-based adaptive binary arithmetic coding (CABAC), and Huffman encoding/decoding; and

and a unit comprising programmable Arithmetic-Logic-Units (ALUs) arranged in a plurality of stages for processing at least one of cosine transforms for video codecs, encoder motion estimation and decoder motion compensation, deblocking filters, scaling filters, adaptive filters, and for picture improvement.

8. The programmable chip according to claim 7, wherein the second processor is programmable.

9. The programmable chip according to claim 8, wherein the second processor comprises a plurality of ALUs arranged in a row.

10. The programmable chip according to claim 8, wherein the second processor has dedicated local memory.

11. The programmable chip according to claim 7, wherein the control processor comprises a plurality of ALUs arranged in a row.

12. The programmable chip according to claim 7, wherein the programmable control processor has dedicated local memory.

13. The programmable chip according to claim 7, wherein the unit has dedicated local memory.

14. The programmable chip according to claim 7, wherein the control processor, the second processor, and the unit are interconnected by a bus structure.