Adaptive Flash Interface

• US 20120017138A1
• Filed: 07/13/2010
• Published: 01/19/2012
• Est. Priority Date: 07/13/2010
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Erez, Eran, Cheng, Steven Shisan
• Granted Patent: US 8,464,135 B2
• Time in Patent Office: Days
• US Class Current: 714/773
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/221 to test buses, lines or interfaces, e.g. stuck-at or open line faults
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A structure, and corresponding operating techniques, are presented for the internal controller to memory circuit interface for memory systems such a flash memory card or other similarly structured devices. The interface between the controller circuit and memory circuit (or circuits) includes a feedback process where the amount of error that arises due to controller-memory transfers is monitored and the transfer characteristics (such as clock rate, drive strength, etc.) can be modified accordingly. For example, in addition to transferring a set of data, the transmitting side also generates and transmits a corresponding hash value for the set of data. When the set of data is received on the other side, a hash value is also generated there and compared to the received hash value to determine if these was transmission error. If there is no error, the transfer rate could, for example, be increased, while if there were error, it could be decreased.

Claims

1. A non-volatile memory system, comprising:

a controller circuit, including a memory interface and logic circuitry;

a memory circuit, including an array of non-volatile memory cells, a controller interface, and logic circuitry;

a bus structure connected to the memory interface of the controller circuit and to the controller interface of the memory circuit for the transfer of data and commands therebetween; and

a feedback processing circuit connected to the logic circuitry of the receiving one the controller and the memory circuit during a transfer of data therebetween to receive information on the amount of error occurring as a result of the transfer, and connected to one or both of the memory interface and the controller interface to adjust the characteristics of the transfer therebetween in response to the amount of error.

2. The non-volatile memory system of claim 1, wherein said transfer of data is from the controller circuit to the memory circuit.

3. The non-volatile memory system of claim 1, wherein said transfer of data is from the memory circuit to the controller circuit.

4. The non-volatile memory system of claim 1, wherein the logic circuitry of each of the controller and the memory circuit include a hash value generator,

wherein in the transfer process from the first one of the memory circuit and the controller to the second one thereof, the first transmits over the bus structure a data set and a first hash value generated from the data set by first one'"'"'s logic circuit, and the second one receives from the bus structure the data set and the first hash value and generates from the received data set a second hash value from the data set by second one'"'"'s logic circuit, and

wherein the logic circuitry of the second one of the memory circuit and the controller further includes comparison circuit connected to receive and perform a comparison of the first hash value as received and the second hash value, said amount of error being based on the result of the comparison.

5. The non-volatile memory system of claim 4, wherein the circuitry used for generating the respective hash values on the memory circuit and the controller are equivalent.

6. The non-volatile memory system of claim 4, wherein the circuitry used for generating the respective hash values on the memory circuit and the controller are not equivalent.

7. The non-volatile memory system of claim 1, wherein the comparison determines whether or not the first and second hash values are equal, and, in response to determining that the first and second values are not equal, the logic of circuitry of the second one of the memory circuit and the controller further quantifies the amount of error.

8. The non-volatile memory system of claim 1, wherein the feedback processing circuit is formed on the same integrated circuit as the controller.

9. The non-volatile memory system of claim 1, wherein the feedback processing circuit is formed on the same integrated circuit as the memory circuit.

10. The non-volatile memory system of claim 1, wherein the feedback processing circuit is formed on a separate integrated circuit from both of the controller and the memory circuit.

11. The non-volatile memory system of claim 1, wherein the memory circuit is formed of a plurality of integrated circuits, each including an array of non-volatile memory cells, a controller interface, and logic circuitry.

12. The non-volatile memory system of claim 11, wherein each integrated circuit of the memory circuit is connected to the controller by a distinct bus.

13. The non-volatile memory system of claim 11, wherein one or more of integrated circuit of the memory circuit are connected to the controller by a shared bus.

14. The non-volatile memory system of claim 11, wherein characteristics of the transfer between the controller and a plurality of the integrated circuits of the memory circuit can be independently adjusted.

15. A method of operating a non-volatile memory system including a controller circuit and a non-volatile memory circuit, the method comprising:

generating a first hash value from a data set in logic circuitry on a first of the controller circuit and the memory circuit;

transmitting to a bus structure the data set and the first hash value through an interface on the first of the controller circuit and the memory circuit;

receiving the data set and the first hash value from the bus structure through an interface on the second of the controller circuit and the memory circuit generating a second hash value from the data set as received in logic circuitry on the second of the controller circuit and the memory circuit;

comparing the first hash value as received and the second hash value on the second of the controller circuit and the memory circuit; and

based on the comparison of the first hash value as received and the second hash value by the logic circuitry on the second of the controller circuit and the memory circuit, determining whether to alter characteristics of the transfer of data between the controller circuit and the memory circuit.

16. The method of claim 15, wherein the first of the controller circuit and the memory circuit is the controller circuit.

17. The method of claim 15, wherein the first of the controller circuit and the memory circuit is the memory circuit.

18. The method of claim 15, wherein the logic circuitry used for generating the respective hash values on the memory circuit and the controller are equivalent.

19. The method of claim 15, wherein the logic circuitry used for generating the respective hash values on the memory circuit and the controller are not equivalent.

20. The method of claim 15, wherein the characteristics of the transfer of data between the controller circuit and the memory circuit include a frequency at which data is transferred.

21. The method of claim 15, wherein the characteristics of the transfer of data between the controller circuit and the memory circuit include a clock frequency for the bus structure.

22. The method of claim 15, wherein the characteristics of the transfer of data between the controller circuit and the memory circuit include a slew rate used in the transfer.

23. The method of claim 15, wherein the characteristics of the transfer of data between the controller circuit and the memory circuit include an interface voltage at which data is transferred.

24. The method of claim 15, wherein the characteristics of the transfer of data between the controller circuit and the memory circuit include a drive strength at which data is transferred.

25. The method of claim 15, wherein the hash values are built based on a cyclic redundancy check.

26. The method of claim 15, wherein the hash values are built based on an error correction code.

27. The method of claim 15, wherein prior transmitting the data set and the first hash value through the interface on the first of the controller circuit and the memory circuit, the characteristics of the transfer of data are set to an initial set of values determined from a look up table based upon the characteristics of the bus structure and the memory circuit of the memory system.

28. The method of claim 15, wherein prior transmitting the data set and the first hash value through the interface on the first of the controller circuit and the memory circuit, the characteristics of the transfer of data are set to an initial set of values determined from a look up table based upon the one or more parameters.

29. The method of claim 15, wherein prior transmitting the data set and the first hash value through the interface on the first of the controller circuit and the memory circuit, the characteristics of the transfer of data are set to an initial set of values determined from the quality of a previous transmission of data between the controller circuit and the memory circuit.

30. The method of claim 29, wherein the one or more parameters include a supply voltage level.

31. The method of claim 29, wherein the one or more parameters include a temperature.

32. The method of claim 29, wherein the one or more parameters include processing values for one or both of the controller circuit and the memory circuit.

33. The method of claim 15, the generating and transmitting of the first hash value is in response to a request from one of the controller circuit and the memory circuit.

34. The method of claim 15, further comprising:

in response to said determining, altering the characteristics of the transfer of data between the controller circuit and the memory circuit. wherein the altering is done symmetrically with respect to transfers from the controller circuit to the memory circuit and transfers from the memory circuit to the controller circuit.

35. The method of claim 15, further comprising:

in response to said determining, altering the characteristics of the transfer of data between the controller circuit and the memory circuit. wherein the altering is done asymmetrically with respect to transfers from the controller circuit to the memory circuit and transfers from the memory circuit to the controller circuit.

36. A method of operating a non-volatile memory system having a controller circuit and a memory circuit including an array of non-volatile memory cells, the method comprising:

transferring a set of data from buffer memory on the controller through transmission circuitry on the controller to a bus structure connecting the controller to the memory circuit;

receiving the set of data from the bus structure through receiving circuitry on the memory circuit;

storing the set of data as received in buffer memory on the memory circuit;

transferring the set of data as stored in buffer memory on the memory circuit, and without being written into the array, through transmission circuitry on the memory circuit to the bus structure;

receiving the set of data from the bus structure through receiving circuitry on the controller;

subsequently storing the set of data as received in buffer memory on the controller;

subsequently adjusting characteristics of the transfer of data between the controller circuit and the memory circuit based upon amount of error the set of data as received and stored in the buffer memory on the controller.

37. The method of claim 36, wherein the amount of error is determined by ECC circuitry on the controller.