MULTI-CORE PROCESSING SYSTEM AND COMPUTER READABLE RECORDING MEDIUM RECORDED THEREON A SCHEDULE MANAGEMENT PROGRAM

• US 20120017217A1
• Filed: 03/24/2011
• Published: 01/19/2012
• Est. Priority Date: 07/13/2010
• Status: Abandoned Application

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Umezawa, Keiichi, Murata, Takehiko
• Application Number:
  US13/070,933
• Publication Number:
  US 20120017217A1
• Time in Patent Office: Days
• US Class Current: 718/102
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms

Abstract

A multi-core processor system has a processing order manager which manages command blocks in a lock acquired state under exclusive control, an assigner which assigns a command block managed by the processing order manager to one of the processor cores, an exclusion manager which manages command blocks in a lock acquisition waiting state under the exclusive control, and a transfer controller which, when the command block in the lock acquisition waiting state managed by the exclusion manager gets into the lock acquired state, releases the command block from the exclusion manager, and registers the command block in the processing order manager, thereby efficiently processing tasks.

Claims

1. A multi-core processor system having a plurality of processor cores and executing a task having a plurality of threads to be implemented in a specific execution order in each of the processor cores, the multi-core processor system comprising:

a processing order manager that manages a command block in a lock acquired state under exclusive control;

an assigner that assigns the command block managed by the processing order manager to one of the processor cores;

an exclusion manager that manages a command block in a lock acquisition waiting state under the exclusive control; and

a transfer controller that, when the command block in the lock acquisition waiting state managed by the exclusion manager gets into the lock acquired state, releases the command block from the exclusion manager, and registers the command block in the processing order manager.

2. The multi-core processor system according to claim 1, wherein the exclusion manager registers each of command blocks in the exclusion manager in order of acceptance of commands from a host;

the transfer controller registers each of the command blocks having been registered in the exclusion manager in the processing order manager in order of entry in the exclusion manager; and

the assigner assigns each of the command blocks to a corresponding processor core in order of entry of the command blocks in the processing order manager.

3. The multi-core processor system according to claim 1, wherein the exclusion manager manages the command blocks corresponding to respective threads, separately.

4. The multi-core processor system according to claim 3 further comprising:

an individual thread exclusion manager that manages command blocks in the lock acquisition waiting state under the exclusive control for each of threads, in order of acceptance of commands from the host;

when the exclusion manager releases a command block, the individual thread exclusion manager registers a command block, which is at a leading position in a queue of command blocks arranged in order of acceptance of commands for a thread corresponding to the released command block, in the exclusion manager.

5. The multi-core processor system according to claim 2 further comprising:

a re-entry processor that re-registers a command block processed in the thread at a leading position in a queue of command blocks in the lock acquisition waiting state in the exclusion manager.

6. The multi-core processor system according to claim 5 further comprising:

a processor information controller that sets processor identification information indicating a processor core to process a command block in the command block; and

the processor information controller sets the processor identification information specifying the processor core having processed the command block in the command block.

7. The multi-core processor system according to claim 6, wherein, when a processor core in a processible state differs from a processor core corresponding to the processor identification information set in the command block, the processor information controller clears the processor identification information set in the command block.

8. The multi-core processor system according to claim 6, wherein a processor core to access to a hardware resource is beforehand specified as an access processor core;

and

the processor information controller sets the processor identification information corresponding to the access processor core to a command block relating to a process in which an access to the hardware resource occurs.

9. The multi-core processor system according to claim 8 further comprising:

a suppression controller that, when the assigner tries to assign a command block to the access processor core but the access processor core corresponding to the command block is in course of execution of another process, suppresses the process by the assigner until the access processor core completes the relevant process.

10. The multi-core processor system according to claim 9 further comprising:

a suppression setting information controller that sets suppression setting information representing whether to make a function by the suppression controller valid or not in the command block.

11. The multi-core processor system according to claim 1 further comprising:

an exclusion controller that sets thread exclusion information representing exclusion setting among threads for the command block in the command block; and

reading of a thread is done based on the thread exclusion information set by the exclusion controller.

12. A computer readable recording medium recorded thereon a schedule management program instructing a computer to execute a scheduling function in a multi-core processor system having a plurality of processor cores and executing a task having a plurality of threads to be implemented in a specific execution order in each of the processor cores;

the schedule management program instructing the computer to function as;

a processing order manager that manages a command block in a lock acquired state under exclusive control;

an assigner that assigns the command block managed by the processing order manager to one of the processor cores;

an exclusion manager that manages a command block in a lock acquisition waiting state under the exclusive control; and

a transfer controller that, when the command block in the lock acquisition waiting state managed by the exclusion manager gets into the lock acquired state, releases the command block from the exclusion manager, and registers the command block in the processing order manager.

13. The computer readable recording medium recorded thereon a schedule management program according to claim 12, wherein the schedule management program registers each of the command blocks in the exclusion manager in order of acceptance of commands from a host when instructing the computer to function as the exclusion manager;

registers each of the command blocks having been registered in the exclusion manager in the processing order manager in order of entry in the exclusion manager when instructing the computer to function as the transfer controller; and

assigns each of the command blocks in the processing order manager to a corresponding processor core in order of entry of the command blocks in the processing order manager when instructing the computer to function as the assigner.

14. The computer readable recording medium recorded thereon a schedule management program according to claim 12, wherein the schedule management program manages command blocks corresponding to respective threads, separately, when instructing the computer to function as the exclusion manager.

15. The computer readable recording medium recorded thereon a schedule management program according to claim 14, wherein the schedule management program instructs the computer to function as an individual thread exclusion manager that manages command blocks in the lock acquisition waiting state under the exclusive control, for each of threads, in order of acceptance of commands from the host;

and

when the exclusion manager releases a command block, the individual thread exclusion manager registers a command block, which is at a leading position in a queue of command blocks arranged in order of acceptance of commands for a thread corresponding to the released command block, in the exclusion manger when instructing the computer to function as the exclusion manager.

16. The computer readable recording medium recorded thereon a schedule management program according to claim 13, wherein the schedule management program instructs the computer to function as:

a re-entry processor that re-registers a command block having been processed in the thread at a leading position in a queue of command blocks in the lock acquisition waiting state in the exclusion manager.

17. The computer readable recording medium recorded thereon a schedule management program according to claim 16, wherein the schedule management program instructs the computer to function as:

a processor information controller that sets processor identification information indicating a processor core to process a command block in the command block; and

the schedule management program sets the processor identification information specifying the processor core having processed the command block in the command block when instructing the computer to function as the processor information controller.

18. The computer readable recording medium recorded thereon a schedule management program according to claim 17, wherein the schedule management program beforehand specifies a processor core to access to a hardware resource as an access processor core;

and

sets the processor identification information corresponding to the access processor core in a command block relating to a process in which an access to the hardware resource occurs when instructing the computer to function as the processor information controller.

19. The computer readable recording medium recorded thereon a schedule management program according to claim 12, wherein the schedule management program instructs the computer to function as an exclusion controller that sets thread exclusion information representing exclusion setting among threads for the command block in the command block;

and

does reading of a thread based on the thread exclusion information set by the exclusion controller.

20. A method for processing a task having a plurality of threads to be implemented in a specific execution order, in processor cores included in a multi-core processor system, comprising:

managing a command block in a lock acquired state under exclusive control using a first managing queue;

assigning the command block managed in the first managing queue to one of the processor cores;

managing a command block in a lock acquisition waiting state under the exclusive control using a second managing queue; and

when the command block in the lock acquisition waiting state managed in the second managing queue gets into the lock acquired state, releasing the command block from the second managing queue, and registering the command block in the first managing queue.