Self-aligned top-gate thin film transistors and method for fabricating same

• US 20120018718A1
• Filed: 11/26/2010
• Published: 01/26/2012
• Est. Priority Date: 07/21/2010
• Status: Abandoned Application

• Current Assignee: National Chiao Tung University (Government of The Republic of China)
• Original Assignee: National Chiao Tung University (Government of The Republic of China)
• Inventors: Zan, Hsiao-Wen, Chen, Wei-Tsung, Chou, Cheng-Wei, Tsai, Chuang-Chuang
• Application Number:
  US12/927,835
• Publication Number:
  US 20120018718A1
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A self-aligned top-gate thin film transistor and a fabrication method thereof. The method includes preparing a substrate having sequentially formed thereon an oxide semiconductor layer, a dielectric layer, and a metallic layer, wherein the oxide semiconductor layer includes first and second connecting regions that are not covered by the dielectric layer and the metallic layer thereon respectively, the first and second connecting regions having a property of a conductor after undergone a heating process or an ultraviolet irradiation; and a source electrode and a drain electrode formed on the substrate and connected to the first and second connecting regions, respectively. Therefore, the contact resistance of the first and second connecting regions can be reduced without the process of ion dopants as required by prior art techniques, thereby simplifying the manufacturing process. Also, the source electrode and the drain electrode can be exactly relocated and further increase performance of the device.

Claims

1. A method for forming a self-aligned top-gate thin film transistor, comprising:

preparing a substrate having sequentially formed thereon an oxide semiconductor layer, a dielectric layer, and a metallic layer, wherein the oxide semiconductor layer is larger in area than the dielectric layer and the metallic layer, and is defined with a first and a second connecting regions that are not covered by the dielectric layer and the metallic layer;

performing a heating process or an ultraviolet irradiation to the first and second connecting regions, with the metallic layer as a mask, to allow the first and second connecting regions to have a property of a conductor; and

forming a source electrode and a drain electrode on the substrate, and electrically connecting the source electrode and the drain electrode to the first and second connecting regions, respectively.

2. The method of claim 1, wherein the oxide semiconductor layer is made of at least a material selected from the group consisting of indium oxide, zinc oxide, gallium oxide, tin oxide and magnesium oxide.

3. The method of claim 1, wherein a wavelength of the ultraviolet radiation is less than 400 nm.

4. The method of claim 1, wherein the heating process is a laser heating process.

5. The method of claim 1, wherein the source electrode and the drain electrode cover the first connecting region and the second connecting region, respectively.

6. A self-aligned top-gate thin film transistor, comprising:

a substrate;

an oxide semiconductor layer formed on the substrate;

a dielectric layer formed on the oxide semiconductor layer, allowing the oxide semiconductor layer to be sandwiched between the substrate and the dielectric layer;

a metal layer formed on the dielectric layer, allowing the dielectric layer to be sandwiched between the oxide semiconductor layer and the metal layer, wherein the oxide semiconductor layer is larger in area than the dielectric layer and the metallic layer, and is defined with a first and a second connecting regions that are not covered by the dielectric layer and the metallic layer, the first and second connecting regions having a property of a conductor;

a source electrode formed on the substrate and electrically connected to the first connecting region; and

a drain electrode formed on the substrate and electrically connected to the second connecting region.

7. The self-aligned top-gate thin film transistor of claim 6, wherein the oxide semiconductor layer is made of at least a material selected from the group consisting of indium oxide, zinc oxide, gallium oxide, tin oxide and magnesium oxide.

8. The self-aligned top-gate thin film transistor of claim 6, wherein the source electrode and the drain electrode cover the first connecting region and the second connecting region, respectively.