Structure And Method For Dual Work Function Metal Gate CMOS With Selective Capping

• US 20120018810A1
• Filed: 01/13/2011
• Published: 01/26/2012
• Est. Priority Date: 01/13/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Niimi, Hiroaki, Chambers, James Joseph
• Granted Patent: US 8,536,654 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A CMOS device having an NMOS transistor with a metal gate electrode comprising a mid-gap metal with a low work function/high oxygen affinity cap and a PMOS transistor with a metal gate electrode comprising a mid gap metal with a high work function/low oxygen affinity cap and method of forming.

Claims

1. A device comprising:

an NMOS transistor with a first gate dielectric, first mid-gap metal gate, and a first cap layer, wherein the first cap layer comprises a material having a high oxygen affinity and low work function; and

a PMOS transistor with a second gate dielectric, second mid-gate metal gate and a second cap layer, wherein the second cap layer comprises a material having a low oxygen affinity and high work function.

2. The device of claim 1, wherein the first mid-gap metal gate has a lower oxygen concentration than the second mid-gap metal gate and wherein low work function material from the first cap layer is incorporated at an interface between the first mid-gap metal gate and the first gate dielectric.

3. The device of claim 1, wherein the first cap layer comprises Al.

4. The device of claim 1, wherein the first cap layer comprises a material selected from the group consisting of Al, Ti, Ta, Y, Hf, and lanthides.

5. The device of claim 1, wherein the second cap layer comprises W.

6. The device of claim 1, wherein the second cap layer is selected from the group consisting of W, Mo, Pt, Re, and Ir.

7. The device of claim 1, wherein the NMOS transistor further comprises the second cap layer separated from the first mid-gap metal gate by the first cap layer.

8. The device of claim 1, wherein the PMOS device further comprises the first cap layer separated from the second mid-gap metal gate by the second cap layer.

9. The device of claim 1, wherein the first mid-gap metal gate and the second mid-gap metal gate comprise the same mid-gap metal.

10. A method of forming a device, comprising the steps of:

providing a semiconductor body having a NMOS gate stack, a PMOS gate stack, and an oxide layer formed thereon, wherein the NMOS gate stack comprises a first gate dielectric, a first mid-gap metal gate, and a first dummy poly layer and the PMOS gate stack comprises a second gate dielectric, a second mid-gap metal gate, and a second dummy poly layer;

removing the first dummy poly;

forming a first cap layer over the first mid-gap metal gate, the first cap layer comprising a high oxygen affinity and low work function material;

removing the second dummy poly;

forming a second cap layer over the second mid-gap metal gate, the second cap layer comprising a low oxygen affinity and high work function material;

after removing the second dummy poly and prior to forming the second cap layer, performing a low temperature oxidation to incorporate oxygen into the second mid-gap metal gate; and

annealing to incorporate low work function material from the first cap layer into the first mid-gap metal gate at the interface between the first mid-gap metal gate and the first gate dielectric.

11. The method of claim 10, wherein the first cap layer comprises Al.

12. The method of claim 10, wherein the second cap layer comprises W.

13. The method of claim 10, wherein the first cap layer comprises a material selected from the group consisting of Al, Ti, Ta, Y, Hf, and lanthides and wherein the second cap layer is selected from the group consisting of W, Mo, Pt, Re, and Ir.

14. The method of claim 10, wherein the second dummy poly is removed prior to removing the first dummy poly.

15. The method of claim 10, wherein the step of forming the second cap layer comprises:

depositing the second cap layer over both the NMOS gate stack and the PMOS gate stack; and

removing the second cap layer from the NMOS gate stack;

and wherein the step of forming the first cap layer comprises;

after removing the second cap layer from the NMOS gate stack, depositing the first cap layer over both the NMOS gate stack and the second cap layer of the PMOS gate stack.

16. The method of claim 15, wherein the second cap layer is a thin cap layer compared to the first cap layer.

17. A method of forming a device, comprising the steps of:

providing a semiconductor body having a NMOS gate stack, a PMOS gate stack, and an oxide layer formed thereon, wherein the NMOS gate stack comprises a first gate dielectric, a first mid-gap metal gate, and a first dummy poly layer and the PMOS gate stack comprises a second gate dielectric, a second mid-gap metal gate, and a second dummy poly layer;

removing the first dummy poly layer and the second dummy poly layer;

performing a low temperature oxidation to incorporate oxygen into the first mid-gate metal gate and the second mid-gap metal gate;

depositing a first cap layer over the NMOS gate stack and the PMOS gate stack;

removing the first cap layer from one of the NMOS gate stack and PMOS gate stack;

depositing a second cap layer over both the NMOS gate stack and the PMOS gate stack, wherein one of the first cap layer and the second cap layer comprise a low oxygen affinity and high work function material and the other comprises a high oxygen affinity and low work function material such that oxygen is scavenged from the first mid-gap metal gate; and

after depositing the second cap layer, annealing the device to incorporate low work function material into the first mid-gap metal gate at an interface between the first mid-gap metal gate and the first gate dielectric.

18. The method of claim 17, wherein the step of removing the first cap layer from one of the NMOS gate stack and the PMOS gate stack, removes the first cap layer from the NMOS gate stack, and wherein the first cap layer comprises the low oxygen affinity and high work function material while the second cap layer comprises the high oxygen affinity and low work function material.

19. The method of claim 17, wherein the step of removing the first cap layer from one of the NMOS gate stack and the PMOS gate stack, removes the first cap layer from the PMOS gate stack, and wherein the first cap layer comprises the high oxygen affinity and low work function material while the second cap layer comprises the low oxygen affinity and high work function material.