SEMICONDUCTOR APPARATUS HAVING THROUGH VIAS

• US 20120018885A1
• Filed: 12/06/2010
• Published: 01/26/2012
• Est. Priority Date: 07/26/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Cho, Taeje, Kang, Un-Byoung, Kim, Jung-Hwan, Lee, Go Eun, Ryu, Seongmin, Min, Tae Hong
• Granted Patent: US 8,884,416 B2
• Time in Patent Office: Days
• US Class Current: 257/738
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49855 : for flat-cards, e.g. credit cards cards per se G06K19/00
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A semiconductor apparatus includes a base substrate and a logic chip disposed on the base substrate. The logic chip includes a memory control circuit, a first through silicon via, and a second through silicon via. The memory control circuit is disposed on a first surface of a substrate of the logic chip, and a memory chip is disposed on a second surface of the substrate of the logic chip. The first through silicon via electrically connects the memory control circuit and the memory chip, the second through silicon via is electrically connected to the memory chip and is configured to transmit power for the memory chip, the second through silicon via is electrically insulated from the logic chip, and the first surface of the substrate of the logic chip faces the base substrate.

Claims

1. A semiconductor apparatus, comprising:

a base substrate;

a logic chip disposed on the base substrate, the logic chip including a memory control circuit, a first through silicon via, and a second through silicon via, the memory control circuit disposed on a first surface of a substrate of the logic chip; and

a memory chip disposed on a second surface of the substrate of the logic chip,

wherein the first through silicon via electrically connects the memory control circuit and the memory chip, the second through silicon via is electrically connected to the memory chip and configured to supply power to the memory chip, the second through silicon via is electrically insulated from the logic chip, and the first surface of the substrate of the logic chip faces the base substrate.

2. The semiconductor apparatus of claim 1, wherein a plurality of conductive solder balls are disposed between the memory chip and the logic chip and between the logic chip and the base substrate.

3. The semiconductor apparatus of claim 2, wherein each conductive solder ball is disposed on respective conductive pads.

4. The semiconductor apparatus of claim 1, further comprising:

an interlayer dielectric layer disposed on the first surface of the substrate of the logic chip.

5. The semiconductor apparatus of claim 4, wherein at least an internal wiring is disposed in the interlayer dielectric layer configured to electrically connect the memory control circuit and a conductive pad having a conductive solder ball thereon.

6. The semiconductor apparatus of claim 1, wherein at least a redistribution line is disposed on the second surface of the substrate of the logic chip.

7. The semiconductor apparatus of claim 1, wherein an external input/output circuit, a micro input/output circuit, and an additional function circuit are disposed on the first surface of substrate of the logic chip.

8. The semiconductor apparatus of claim 1, wherein the base substrate comprises at least a circuit pattern therein.

9. The semiconductor apparatus of claim 1, wherein the first through silicon via is configured to supply a data signal and a control signal to the memory chip.

10. The semiconductor apparatus of claim 1, wherein the power comprises a power voltage (VDD) and a ground voltage (VSS).

11. The semiconductor apparatus of claim 1, wherein the logic chip comprises a mobile CPU.

12. The semiconductor apparatus of claim 1, wherein the memory chip comprises a wide I/O memory or a flash memory.

13. The semiconductor apparatus of claim 1, wherein a molding compound is disposed on the logic chip and the memory chip.

14. The semiconductor apparatus of claim 1, wherein the base substrate comprises a printed circuit board (PCB).

15. The semiconductor apparatus of claim 1, further comprising:

an interposer disposed either between the logic chip and the base substrate or between the logic chip and the memory chip.

16. The semiconductor apparatus of claim 1, further comprising:

an additional memory chip disposed between the logic chip and the memory chip, the additional memory chip comprising at least one through silicon via.

17. The semiconductor apparatus of claim 1, further comprising:

a third through silicon via immediately adjacent to the first through silicon via and electrically connected to the first through silicon via.

18. The semiconductor apparatus of claim 17, further comprising:

a fourth through silicon via immediately adjacent to the second through silicon via and electrically connected to the second through silicon via.

19. The semiconductor apparatus of claim 1, wherein the first through silicon via comprises a conductive connection surrounded by a via insulation layer.

20. An arrangement of semiconductor chips, the arrangement comprising:

a base substrate;

a logic chip disposed on the base substrate, the logic chip including a memory control circuit disposed on a first surface of a substrate of the logic chip; and

a memory chip disposed on a second surface of the substrate of the logic chip,

wherein a signal between the logic chip and the memory chip transmits through a first path and a power for the memory chip transmits through a second path, the first path is electrically insulated from the second path, and the first surface of the substrate of the logic chip faces the base substrate.

21. The arrangement of semiconductor chips of claim 20, wherein the first path comprises a first through silicon via, a micro input/output circuit, a memory control circuit, and an external input/output circuit.

22. The arrangement of semiconductor chips of claim 21, wherein the second path comprises a second through silicon via.

23. A semiconductor apparatus, comprising:

a base substrate;

a logic chip disposed on the base substrate, the logic chip including a memory control circuit, an I/O circuit, a first through silicon via configured to transmit signals, and a second through silicon via configured to transmit power, the memory control circuit disposed on a first surface of a substrate of the logic chip; and

a memory chip disposed on a second surface of the substrate of the logic chip,

wherein the I/O circuit is electrically connected between the memory control circuit and the first through silicon via through metal connections, the I/O circuit includes channels for transmitting a data signal, a control signal, power voltage (Vdd), and ground voltage (Vss).

24. A semiconductor apparatus, comprising:

a base substrate;

a logic chip disposed on the base substrate, the logic chip including a plurality of circuits and a plurality of through silicon vias; and

a memory chip stacked on the logic chip in a first direction, the through silicon vias oriented in the first direction,

wherein the memory chip overlaps the plurality of through silicon vias, the plurality of circuits do not overlap the plurality of through silicon vias, and the memory chip overlaps at least one circuit.

25. A semiconductor module, comprising:

a PCB substrate including a plurality of circuit patterns disposed thereon and a plurality of external device terminals disposed at respective ends of the circuit patterns; and

a semiconductor apparatus disposed on and electrically connected to the PCB substrate through the plurality of circuit patterns, the semiconductor apparatus including,

a logic chip including a memory control circuit and a plurality of through silicon vias, and

a memory chip disposed on the logic chip, the plurality of through silicon vias configured to transmit power or signals to the memory chip;

wherein the external device terminals are configured to receive signals other than a memory control signal.

26. The semiconductor module of claim 25, wherein the external device terminals are configured to receive at least one of a logic signal, a logic power, or a memory power.