MICROELECTRONIC DEVICE PACKAGES, STACKED MICROELECTRONIC DEVICE PACKAGES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES

• US 20120018887A1
• Filed: 10/03/2011
• Published: 01/26/2012
• Est. Priority Date: 08/26/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ye, Seng Kim Dalson, Chong, Chin Hui
• Granted Patent: US 8,519,523 B2
• Time in Patent Office: Days
• US Class Current: 257/738
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/4382 Applying permanent coating, e.g. in-situ coating
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06575 Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1088 : Arrangements to limit the height of the assembly
• CPC Class Codes: H01L 23/13 : characterised by the shape
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 25/00 : Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereofdevices consisting of a plurality of solid state components formed in or on a common substrate H01L27/00; photovoltaic modules or arrays of photovoltaic cells H01L31/042 ; panels or arrays of photo electrochemical cells H01G9/2068
• CPC Class Codes: H01L 25/043 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/074 : Stacked arrangements of non-apertured devices
• CPC Class Codes: H01L 25/0756 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/10 : the devices having separate containers
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/117 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic die is attached to the first die on one side, and to a second substrate on the other side. Electrical connections are made between the first die and the first substrate, between the second die and the second substrate, and between the first and second substrates, e.g., via wire bonding. The electrical connecting elements are advantageously encased in a molding compound. Exposed contacts on the first and/or second substrates, not covered by the molding compound, provide for electrical connections between the package, and another package stacked onto the package. The package may avoid coplanarity factors, can be manufactured using existing equipment, allows for intermediate testing, and can also offer a thinner package height.

Claims

1. A microelectronic package, comprising:

a first substrate;

a first microelectronic die electrically connecting with the first substrate;

a second substrate electrically connecting with the first substrate; and

a second microelectronic die electrically connecting to the second substrate.

2. The microelectronic package of claim 1 further including a first set of wires connecting a second side of the first substrate to a second side of the second substrate;

a second set or wires connecting a first side of the first substrate to a central area of the first microelectronic die; and

a third set of wires connecting the second side of the second substrate to the second microelectronic die.

3. The microelectronic package of claim 1 wherein the first substrate is larger than the second substrate.

4. The microelectronic package of claim 3 with the first substrate is electrically connected to the second substrate via wire bonding.

5. The microelectronic package of claim 1 wherein the first microelectronic die comprises a board-on-chip package construction.

6. The microelectronic package of claim 1 wherein the second microelectronic die comprises a board-on-chip package construction.

7. The microelectronic package of claim 1 with the second substrate having an exposed grid array of electrical contacts to allow for a stacking assembly of two or more package assemblies.

8. The microelectronic package of claim 1 with the first and second microelectronic dies each having an active side including a plurality of active terminals, and a back side, and with the back side of the first microelectronic die attached to the back side of the second microelectronic die.

9. The microelectronic package of claim 1 with the first substrate having a first side and a second side, with the second side adjoining the first microelectronic die, and with the first side of the substrate having a plurality of contacts, and with the first substrate having a through opening, and further comprising wires extending from the plurality of contacts on the first side of the substrate to the first microelectronic die.

10. The microelectronic package of claim 9 with the second substrate having a first side and a second side, with the first side adjoining the second microelectronic die, and with the second substrate having a through opening, and further comprising wires extending from a plurality of contacts on the second die to the second side of the second substrate.

11. The microelectronic package of claim 2 further comprising a mold compound encapsulating the first, second and third sets of wires.

12. The microelectronic package of claim 1 with the first die adjoining the first substrate and with the second die adjoining the second substrate and with the first die adjoining the second die.

13. The microelectronic package of claim 1 with the first die electrically connected to the first die via plurality of electrical terminals on an active side of the first die in contact with a second side of the first substrate.

14. A stacked microelectronic package assembly, comprising:

a first microelectronic package, comprising;

a first substrate;

a first microelectronic die electrically connecting with the first substrate;

a second substrate electrically connecting with the first substrate; and

a second microelectronic die electrically connecting to the second substrate; and

a second microelectronic package, comprising;

a third substrate;

a third microelectronic die electrically connecting with the third substrate; and

a plurality of electrical connections between the second and third substrates.

15. The stacked microelectronic package assembly of claim 14 further comprising:

a first, second and third set of wires associated with the first microelectronic package assembly, with the first set of wires connecting a second side of the first substrate to a second side of the second substrate;

the second set or wires connecting a first side of the first substrate to a central area of the first microelectronic die; and

the third set of wires connecting the second side of the second substrate to the second microelectronic die;

a fourth substrate electrically connecting with the third substrate; and

a fourth, fifth and sixth set of wires associated with the second microelectronic package assembly, with the fourth set of wires connecting a second side of the third substrate to a second side of the fourth substrate;

the fifth set or wires connecting a first side of the third substrate to a central area of the third microelectronic die; and

the sixth set of wires connecting the second side of the fourth substrate to the fourth microelectronic die.

16. The stacked microelectronic package assembly of claim 14 wherein the plurality of electrical connections between the first and second microelectronic package assemblies comprise solder balls between the second and third substrates.

17. The stacked microelectronic package assembly of claim 14 wherein the first substrate is larger than the second substrate.

18. A stackable multi-electronic die package, comprising:

a first die on a first substrate;

a second substrate on a second die;

a spacer between the first and second dies;

a first set of wires connecting the first die to the first substrate;

a second set of wires connecting the second substrate to the first substrate.

19. The stackable multi-electronic die package of claim 18 further comprising a third set of wires connecting the second die to the second substrate via an opening in the second substrate.

20. The stackable multi-electronic die package of claim 18 wherein the first die and first substrate comprise a chip-on-board package construction and the second die and the second substrate comprise a board-on-chip package construction.