RECEPTION APPARATUS

• US 20120020438A1
• Filed: 04/12/2010
• Published: 01/26/2012
• Est. Priority Date: 04/14/2009
• Status: Abandoned Application

• Current Assignee: THine Electronics, Inc.
• Original Assignee: THine Electronics, Inc.
• Inventors: Ozawa, Seiichi
• Application Number:
  US13/263,679
• Publication Number:
  US 20120020438A1
• Time in Patent Office: Days
• US Class Current: 375/340
• CPC Class Codes: H04L 7/0338 the correction of the phase error being performed by a feed forward loop

Abstract

A reception apparatus is an apparatus for receiving serial data and includes a sampler portion, an edge detection portion, a logical addition operation portion, a timing determination portion, a register portion, a selector portion and a latch portion. The edge detection portion inputs data OSD[n] output from the sampler portion, performs an exclusive OR operation between the data OSD[n] and data OSD[n+1] which are adjacent to each other, and outputs data EDG[n] which is the result of the exclusive OR operation. The logical addition operation portion inputs the data EDG[n] output from the edge detection portion, performs, for a predetermined time period, an OR operation on the data EDG[n], with n_o used as a reference value, with respect to each n which leaves a remainder of m when a difference (n−n_o) is divided by a value M, and outputs data EDGFLG[m] which is the result of the OR operation.

Claims

1. A reception apparatus that receives serial data to be input, the reception apparatus comprising:

a sampler portion that samples the serial data at a frequency M times as high as a bit rate of the serial data and that sequentially outputs data OSD[n] obtained by n-th sampling;

an edge detection portion that inputs the data OSD[n] sequentially output from the sampler portion, that performs an exclusive OR operation between the data OSD[n] and data OSD[n+1] which are adjacent to each other, and that outputs data EDG[n] which is a result of the exclusive OR operation;

a logical addition operation portion that inputs the data EDG[n] output from the edge detection portion, that performs, for a predetermined time period, an OR operation on the data EDG[n], with n_o used as a reference value, with respect to each n which leaves a remainder of m when a difference (n−

n_o) is divided by a value M, and that outputs data EDGFLG[m] which is a result of the OR operation;

a timing determination portion that inputs the data EDGFLG[m] output from the logical addition operation portion, that determines a bit transition timing of the serial data based on the data EDGFLG[m], and that outputs data PHSEL[m] which indicates the bit transition timing;

a register portion that inputs the data OSD[n] sequentially output from the sampler portion, that gives a delay of a predetermined time period to the data OSD[n], and that then sequentially outputs the data OSD[n]; and

a selector portion that inputs the data OSD[n] sequentially output from the register portion, that also inputs the data PHSEL[m] output from the timing determination portion and that outputs data OSD[n] which is selected from among the data OSD[n] based on the data PHSEL[m] (where M is an integer of three or more;

m is an integer of zero or more and less than M; and

n is any integer).

2. The reception apparatus of claim 1,

wherein the logical addition operation portion includes:

a first operation portion that inputs the data EDG[n] output from the edge detection portion, that performs, for a given time period, an OR operation on the data EDG[n], with n_o used as a reference value, with respect to each n which leaves a remainder of m when a difference (n−

n_o) is divided by a value M, and that outputs data EDGFLG0[m] which is a result of the OR operation;

a delay portion that inputs the data EDGFLG0[m] output from the first operation portion and that outputs data EDGFLG1[m] which is obtained by giving a delay of the given time period to the data EDGFLG0[m]; and

a second operation portion that inputs the data EDGFLG0[m] output from the first operation portion, that inputs the data EDGFLG1[m] output from the delay portion, that performs an OR operation between the data EDGFLG0[m], and the data EDGFLG1[m] and that outputs data EDGFLG[m] which is a result of the OR operation.

3. The reception apparatus of claim 1,

wherein the logical addition operation portion includes:

a first operation portion that inputs the data EDG[n] output from the edge detection portion, that performs, for a given time period, an OR operation on the data EDG[n], with n_o used as a reference value, with respect to each n which leaves a remainder of m when a difference (n−

n_o) is divided by a value M, and that outputs data EDGFLG0[m] which is a result of the OR operation;

a delay portion that inputs the data EDGFLG0[m] output from the first operation portion and that outputs data EDGFLG1[m] which is obtained by giving a delay of the given time period to the data EDGFLG0[m];

a second delay portion that inputs the data EDGFLG1[m] output from the first delay portion and that outputs data EDGFLG2[m] which is obtained by giving a delay of the given time period to the data EDGFLG1[m]; and

a second operation portion that inputs the data EDGFLG0[m] output from the first operation portion, that inputs the data EDGFLG1[m] output from the first delay portion, that inputs the data EDGFLG2[m] output from the second delay portion, that performs an OR operation among the data EDGFLG0[m], the data EDGFLG1[m] and the data EDGFLG2[m], and that outputs data EDGFLG[m] which is a result of the OR operation.

4. The reception apparatus of claim 1,

wherein the timing determination portion determines the bit transition timing of the serial data in a center value of distribution of the data EDGFLG[m] output from the logical addition operation portion, and outputs the data PHSEL[m] indicating the bit transition timing.

5. The reception apparatus of claim 1,

wherein, when there are two or more pieces of data that are a value of 1 among the data EDGFLG[m] output from the logical addition operation portion, the timing determination portion determines the bit transition timing of the serial data on one of the two or more pieces of data that is close to a bit transition timing indicated by the prior data PHSEL[m], and outputs data PHSEL[m] indicating this bit transition timing.