Nonvolatile Memory System

• US 20120023284A1
• Filed: 09/12/2011
• Published: 01/26/2012
• Est. Priority Date: 02/09/2007
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Chi-Kong Lee, Lau Nguyen, Pantas Sutardja, Tony Yoon, Zining Wu
• Inventors: Wu, Zining, Nguyen, Lau, Sutardja, Pantas, Lee, Chi-Kong, Yoon, Tony
• Granted Patent: US 8,219,775 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0661 Format or protocol conversion arrangements
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

A memory system including a nonvolatile memory, and a memory control module. The nonvolatile memory includes a plurality of memory cells arranged among a plurality of physical memory blocks, wherein each physical memory block is of a predetermined size. The memory control module includes a write path module and a read path module. In response to the memory control module receiving data in a first format such that the data is evenly distributable among the plurality of physical memory blocks, the write path module modifies the first format of the data into a second format prior to writing the data to the plurality of physical memory blocks. The second format of the data is such that the data is no longer evenly distributable among the plurality of physical memory blocks. The read path module is configured to read the data from the nonvolatile memory in accordance with the second format.

Claims

1. A memory system comprising:

a nonvolatile memory including a plurality of memory cells arranged among a plurality of physical memory blocks, wherein each physical memory block is of a predetermined size; and

a memory control module in communication with the nonvolatile memory, wherein the memory control module includes

a write path module, wherein in response to the memory control module receiving data in a first format such that the data is evenly distributable among the plurality of physical memory blocks, the write path module is configured to modify the first format of the data into a second format prior to writing the data to the plurality of physical memory blocks, and wherein the second format of the data is such that the data is no longer evenly distributable among the plurality of physical memory blocks, and

a read path module configured to read the data from the nonvolatile memory in accordance with the second format.

2. The memory module of claim 1, wherein the write path module is configured to increase an error correction code (ECC) rate of the data responsive to modifying the first format of the data into the second format.

3. The memory module of claim 2, wherein the read path module comprises an error correction code (ECC) decoder configured to decode the data from the nonvolatile memory in accordance with the second format.

4. The memory module of claim 3, wherein the error correction code (ECC) decoder comprises one or more of a Low Density Parity Check (LDPC) decoder, a Gray Code decoder, a Bose-Chaudhuri-Hocquenghem (BCH) decoder, a Reed-Solomon decoder, or a cyclic redundancy (CRC) decoder.

5. The memory module of claim 1, wherein the write path module is further configured to modify the first format of the data into a plurality of different formats, including the second format, wherein each different format corresponds to a different error correction code (ECC) rate.

6. The memory module of claim 1, wherein the nonvolatile memory comprises one or more of flash memory, static random access memory (SRAM), phase change memory, magnetic RAM, or multi-state memory.

7. A solid state nonvolatile memory drive comprising the memory module of claim 1, wherein the solid state nonvolatile memory drive is configured to communicate with a host device.

8. A method for operating a memory system, wherein the memory system includes

i) a nonvolatile memory including a plurality of memory cells arranged among a plurality of physical memory blocks, wherein each physical memory block is of a predetermined size;

and

ii) a memory control module in communication with the nonvolatile memory, and

wherein the method includes;

in response to the memory control module receiving data in a first format such that the data is evenly distributable among the plurality of physical memory blocks, modifying the first format of the data into a second format prior to writing the data to the plurality of physical memory blocks, wherein the second format of the data is such that the data is no longer evenly distributable among the plurality of physical memory blocks, and

reading the data from the nonvolatile memory in accordance with the second format.

9. The method of claim 8, wherein modifying the first format of the data into the second format comprises increasing an error correction code (ECC) rate of the data responsive.

10. The method of claim 9, wherein reading the data from the nonvolatile memory in accordance with the second format comprises:

decoding the data from the nonvolatile memory in accordance with the second format.

11. The method of claim 8, wherein modifying the first format of the data into the second format comprises modifying the first format of the data into one of a plurality of different formats, including the second format, wherein each different format corresponds to a different error correction code (ECC) rate.

12. The method of claim 8, wherein the nonvolatile memory comprises one or more of flash memory, static random access memory (SRAM), phase change memory, magnetic RAM, or multi-state memory.