PROTOCOL INCLUDING A COMMAND-SPECIFIED TIMING REFERENCE SIGNAL

• US 20120023363A1
• Filed: 05/11/2011
• Published: 01/26/2012
• Est. Priority Date: 07/22/2010
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Shaeffer, Ian, Giovannini, Thomas J.
• Granted Patent: US 9,665,507 B2
• Time in Patent Office: Days
• US Class Current: 714/6.11
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1093 Input synchronization
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device.

Claims

1. A method of operation in a memory controller, the method comprising:

transmitting a read command which specifies that a memory device output data accessed from a memory core, the read command containing information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data; and

receiving the timing reference signal if the information specified that the memory device output the timing reference signal, wherein the memory controller samples the data output from the memory device based on information provided by the timing reference signal output from the memory device.

2. The method of claim 1, wherein the memory controller samples the data output from the memory device using the timing reference signal if the information specified that the memory device output the timing reference signal.

3. The method of claim 1, wherein the memory controller samples the data output from the memory device using a sampling clock wherein, the method further comprising adjusting the sampling clock based on phase information derived from the timing reference signal.

4. The method of claim 3, further comprising:

after receiving the timing reference signal, receiving an error detection and correction (EDC) signal from the memory device, wherein a first bit of the EDC signal is received after a first bit of the read data; and

using the EDC signal to further update the phase of the internal receive clock after the timing reference signal.

5. The method of claim 1, wherein the read command further includes information that specifies a burst length of the timing reference signal.

6. The method of claim 5, wherein the method further comprises:

determining a duration of an idle period that transpires prior to transmitting the read command to the memory device; and

selecting the information that specifies the burst length based on the duration of the idle period.

7. The method of claim 1, further comprising transmitting a command, to the memory device, that specifies storing a value in a register of the memory device, the value being representative of a burst length of the timing reference signal.

8. The method of claim 1, wherein a burst length of the timing reference signal is the same as a burst length of the data.

9. The method of claim 1, wherein transmitting the read command further comprises:

determining whether the memory device is to be accessed after a predetermined idle period for the memory device transpires; and

specifying that the memory device output the timing reference signal associated with the read command based on the predetermined idle period transpiring.

10. The method of claim 9, wherein the predetermined idle period is of a first duration, the method further comprising:

detecting that the memory device is to be accessed after an idle period transpires that includes a duration longer than the first duration; and

specifying that the memory device output a subsequent timing reference signal having a burst length that is longer than a burst length of the timing reference signal associated with the read command based on the predetermined idle period transpiring.

11. The method of claim 1, wherein the information identifies a selected programmable register from a plurality of programmable registers, disposed on the memory device, that store a corresponding plurality of burst length values that define a selected burst length for the timing reference signal.

12. The method 1, further comprising:

detecting that a predetermined time period has transpired in which an operational state of a memory device is idle;

transmitting a command which specifies that the memory device output a timing reference signal having a predetermined burst length; and

receiving the timing reference signal, wherein the memory controller uses phase information provided by the timing reference signal output from the memory device to adjust a phase of an internal sampling clock used to sample data provided by the memory device.

13. The method of claim 12, wherein the predetermined time period is detected directly prior to transmitting a write command to the memory device.

14. A memory controller, comprising:

a transmitter circuit to provide a read command which specifies that a memory device output data accessed from a memory core, the read command containing information which specifies whether the memory device is to commence output of a timing reference signal prior to outputting of the data; and

a receiver circuit to receive the timing reference signal wherein the timing reference signal is used to adjust memory controller receive timing of the data output from the memory device.

15. The memory controller of claim 14, further comprising a circuit, coupled to the receiver circuit, to generate a sampling clock used to sample the data output from the memory device, the circuit to adjust the sampling clock based on phase information derived from the timing reference signal.

16. The memory controller of claim 15, further comprising:

a receiver circuit to receive an error detection and correction (EDC) signal from the memory device; and

a circuit to update the sampling clock based on information derived from the EDC signal.

17. The memory controller of claim 14, wherein the read command further includes information that specifies a burst length of the timing reference signal.

18. The memory controller of claim 14, wherein the transmitter circuit transmits a command that specifies storing a value in a register of the memory device, the value being representative of a burst length of the timing reference signal.

19. The memory controller of claim 14, wherein the information identifies a selected programmable register from a plurality of programmable registers, disposed on the memory device, that store a corresponding plurality of burst length values that define a selected burst length for the timing reference signal.

20. The memory controller of claim 14, wherein the transmitter circuit provides a command which specifies that the memory device output a timing reference signal having a predetermined burst length.

21. A method for operation of a memory device, the method comprising:

receiving a read command which specifies that the memory device output data accessed from a memory core, the read command containing information which specifies whether the memory device is to commence output of a timing reference signal prior to commencing outputting of the data; and

transmitting the timing reference signal if the information specified that the memory device output the timing reference signal, wherein a memory controller samples the data output from the memory device based on information provided by the timing reference signal output from the memory device.

22. The method of claim 21, further comprising:

generating an error detection and correction signal; and

after transmitting the timing reference signal, transmitting the EDC signal, wherein a first bit of the EDC signal is transmitted after a first bit of the read data is output.

23. The method of claim 21, wherein the read command further includes information that specifies a burst length of the timing reference signal.

24. The method of claim 21, further comprising receiving a command that specifies storing a value in a register of the memory device, the value being representative of a burst length of the timing reference signal.

25. The method of claim 21, wherein the information identifies a selected programmable register from a plurality of programmable registers, disposed on the memory device, that store a corresponding plurality of burst length values that define a selected burst length for the timing reference signal.

26. The method of claim 21, further comprising:

detecting that a predetermined time period has transpired in which an operational state of a memory device is idle; and

transmitting a timing reference signal after detecting that the predetermined time period has transpired.

27. The method of claim 21, further comprising:

receiving a command which specifies that the memory device output a timing reference signal having a predetermined burst length; and

transmitting the timing reference signal in response to the command which specifies that the memory device output the timing reference signal.

28. The method of claim 21, wherein the memory controller uses phase information provided by the timing reference signal output from the memory device to adjust a phase of an internal sampling clock used to sample data provided by the memory device.

29. The method of claim 21, further comprising transmitting a timing reference signal based on a state of an internal state machine.

37. The memory device of claim 21, further comprising:

a circuit to detect that a predetermined time period has transpired in which an operational state of a memory device is idle, wherein the transmitter circuit transmits a timing reference signal after detecting that the predetermined time period has transpired.

30. A memory device, comprising:

a receiver circuit to receive a read command, wherein the read command includes information that specifies whether to precede outputting of data associated with the read command with a timing reference signal; and

a transmitter circuit to output the timing reference signal according to the information.

31. The memory device of claim 30, further comprising a first register to store a value that is representative of a first burst length of the timing reference signal.

32. The memory device of claim 31, further comprising a second register to store a value that is representative of a second burst length of the timing reference signal, wherein the information specifies at least one of the first and second burst lengths for the timing reference signal output by the transmitter, by selecting at least one of the first and second registers, wherein the transmitter circuit outputs the timing reference signal having a burst length as selected by at least the first and second register.

33. The memory device of claim 30, further comprising a plurality of programmable registers, disposed on the memory device, that store a corresponding plurality of burst length values that define a selected burst length for the timing reference signal wherein the information further selects a burst length value for the timing reference signal by addressing a corresponding register of the plurality of registers.

34. The memory device of claim 30, further comprising:

a first transmitter circuit to output the data; and

a second transmitter circuit to output an error detection and correction signal after a first bit of the read data is output by the first transmitter circuit.

35. The memory device of claim 30, wherein the read command further includes information that specifies a burst length of the timing reference signal.

36. The memory device of claim 30, further comprising a register, wherein the receiver circuit receives a command that specifies storing a value in the register, the value being representative of a burst length of the timing reference signal.

38. The memory device of claim 30, wherein the receiver circuit receives a command which specifies that the memory device output a timing reference signal having a predetermined burst length.

39. The memory device of claim 30, further comprising a register that specifies whether the transmitter circuit provides one of the timing reference signal in a first mode and an error detection code in a second mode.

40. The memory device of claim 30, further comprising:

a register that specifies a timing interval between the outputting of the timing signal and outputting a first bit of the data.

41. The memory device of claim 30, further comprising a register that specifies a timing interval to occur between outputting a first bit of the data and transmitting an error detection code, the error detection code corresponding to the data.

42. A memory system, comprising:

a memory device and a memory controller;

a first interconnect to carry a read command from the memory controller to the memory device, the read command including information which specifies whether the memory device is to commence output of a timing reference signal prior to commencing outputting of the data; and

a second interconnect to convey the timing reference signal from the memory device to the memory controller, wherein the timing reference signal is used to adjust memory controller receive timing of the data output from the memory device.

43. The system of claim 42, further comprising a plurality of ranks, wherein the memory device is disposed a rank in the plurality of ranks, wherein the memory controller specifies that the memory device output the timing reference signal associated with the read command after a predetermined idle period transpires for the rank.

44. The system of claim 43, wherein the memory controller specifies that a memory device from each rank of the plurality of ranks output a timing signal periodically in accordance with a corresponding predetermined idle duration for each rank of the plurality of ranks.

45. The system of claim 44, wherein the memory controller schedules read accesses to the plurality of ranks such that a memory device from each rank of the plurality of ranks outputs a timing signal, during each read access, such that a predetermined threshold idle period for each rank is not exceeded.